This work is focused on the design and experimental validation of the all-SiC active neutral-point clamped (ANPC) submodule for an advanced electric vehicle (EV) charging station. The topology of the station is based on a three-wire bipolar DC bus (±750 V) connecting an ac grid converter, isolated DC-DC converters, and a non-isolated DC-DC converter with a battery energy storage. Thus, in all types of power converters, the same three-level submodule may be applied. In this paper, a submodule rated at 1/3 of the nominal power of the grid converter (20 kVA) is discussed. In particular, four different modulation strategies for the 1.5 kV ANPC submodule, exclusively employing fast silicon carbide (SiC) MOSFETs, are considered, and their impact on the submodule performance is analyzed. Moreover, the simulation study is included. Finally, the laboratory prototype is described and experimentally verified at a switching frequency of 64 kHz. It is shown that the system can operate with all of the modulations, while techniques PWM2 and PWM3 emerge as the most efficient, and alternating between them, depending on the load, should be considered to maximize the efficiency. Furthermore, the results showcase that the impact of the different PWM techniques on switching oscillations, including overvoltages, can be nearly fully omitted for a parasitic inductance optimized circuit, and the choice of modulation should be based on power loss and/or other factors.

This article discusses an active gate driver for a 1.7 kV/325 A SiC MOSFET module. The main purpose of the driver is to adjust the gate voltage in specified moments to speed up the turn-on cycle and reduce the amount of dissipated energy. Moreover, an adequate manipulation of the gate voltage is necessary as the gate current should be reduced during the rise of the drain current to avoid overshoots and oscillations. The gate voltage is switched at the right moments on the basis of the feedback signal provided from a measurement of the voltage across the parasitic source inductance of the module. This approach simplifies the circuit and provides no additional power losses in the measuring circuit. The paper contains the theoretical background and detailed description of the active gate driver design. The model of the parasitic-based active gate driver was verified using the double-pulse procedure both in Saber simulations and laboratory experiments. The active gate driver decreases the turn-on energy of a 1.7 kV/325 A SiC MOSFET by 7% comparing to a conventional gate driver (VDS = 900 V, ID = 270 A, RG = 20 Ω). Furthermore, the proposed active gate driver lowered the turn-on cycle time from 478 to 390 ns without any serious oscillations in the main circuit.