The architecture design for statistical operations to compute the Mean, Variance, Standard Deviation, RMS (Root Mean Square), Covariance, and MSE (Mean Square Error) values has been implemented on hardware concerning Xilinx Spartan 3E XC3S500E FPGA and worked properly up to maximum frequency of 73.252 MHz . The practical outcomes have been compared with the theoretical values calculated by Matlab with maximum error of 1.425%. New methods of design were concerned for the architecture of each function to reduce the number of slices. General Terms

Nowadays, the mobile robot can be seen in different fields of engineering and science. The mobile robot can do some tasks that are so difficult or very risky to be performed by a human. Most of the works currently focus on implementing artificially intelligent algorithms and other algorithms that depend on the behaviour of nature. These approaches have been used in mobile robot navigation along uncertain manner. Mobile robot navigation strategies can be divided into two approaches: the classical approach and reactive approach. The classical approach related to static environment, whiles the reactive navigation is based on an unstructured environment. Path planning is one of the most important parts of the navigation system. In this paper, review and assessment of path planning strategies that can concern with the reactive approach are discussed, because it deal with the problem of dynamic environment. Numerous reactive methods have been introduced. Most of these presented works were concerned with simulation and a few of them have shown experimental implementation. Many papers tried to make a combination between two algorithms or more to increase the efficiency. It is concluded that reactive algorithms need more learning phases, complex in design, and require large memory storage.

The autonomous mobile robot must be capable of avoiding static and dynamic obstacles in the environment and navigating towards the target without any human effort. A valid low-cost path from start to goal is obtained by A* algorithm. Neural network used for Zone classification. The relative values between mobile robot and obstacle are used for classification which are distance, velocity, and angle. Zone1 is very dangerous while zone 5 is not dangerous. If the neural network classifies the obstacle as a dangerous obstacle and activates the controller. The fuzzy logic makes a decision as a reaction of mobile robot to prevent collision. There are three inputs to the fuzzy logic (relative velocity, relative distance, and relative angle) between mobile robot and obstacle. The outputs of fuzzy logic are velocity and steering angle of mobile robot. Static obstacles have been added to the environment in addition to dynamic obstacles to make the environment more complex. Three dangerous dynamic obstacles to the mobile robot are tested. While mobile robot is avoiding one obstacle, another obstacle enters critical zone and becomes dangerous to mobile robot. The mobile robot avoids the second obstacle while it is avoiding the first obstacle. Then the velocities of mobile robot and obstacles have been increased to prove that the proposed system can handle cases with faster velocities. The simulation results for the tested cases shows the capability of the proposed method for avoiding static and dynamic obstacles in fully known environment.

In this paper, a pipeline math processor is designed using VHDL, where doing simulation for processor by using simulation program ISE10.1. The processor is implemented on the FPGA chip in a panel SPARTAN3E, where it has been downloaded by using USB port. The register and buffer memory of each of the fetch and decoder units are designed such that reading and writing operations for the same location are performed during one clock cycle (each clock pulse edge is used for one operation). JTAG port is used to update the data and instructions stored in the main memory via monitor circuit. The main memory of the processor contains two ports, one of them is used to update the data and instructions and the other is used to read data and instructions. For the purpose of increasing the speed, decode and execute units are built so that all operations can be executed in parallel. The number of operations that can be executed on the processor are 30 operations including triangular functions, hyperbolic functions, square root, ALU, comparison operations, move operation, and parallel shifting and rotation operations. The number of clocks that is required by the mathematical functions, ranges between 17-23 clocks for the first output and then each clock has it's output when the values of input functions are sequential and continuous. The remaining operations (such as addition, subtraction, multiplication and division) need only one clock for each output. The maximum operating frequency for the design chip was found to be 133.820 MHz, therefore its throughput is 133.820 MFlops. For the purpose of displaying all the processor outputs on a computer screen, the VGA Port is used. The overall design of this processor occupies 98% (when the processor is connected with VGA port) from the volume of the FPGA chip on board SPARTAN3E.

The architectural design of the random number generators for uniform distribution, normal distribution, exponential distribution and Rayleigh distribution using Box-Muller and inverse transformation method has been hardware implemented on FPGA. Any of the random number generators can generate one sample every clock cycle. The generators have been implemented on Xilinx Spartan 3E XC3S500E FPGA. The designed generators work properly up to maximum frequency of 418.41MHz .The outcome results of the generators have been tested by the chi-square test at a 5% level of significance which provided the correct required distributions.