We study terahertz radiation induced ratchet currents in low dimensional semiconductor structures with a superimposed one-dimensional lateral periodic potential. The periodic potential is produced by etching a grating into the sample surface or depositing metal stripes periodically on the sample top. Microscopically, the photocurrent generation is based on the combined action of the lateral periodic potential, verified by transport measurements, and the in-plane modulated pumping caused by the lateral superlattice. We show that a substantial part of the total current is caused by the polarization-independent Seebeck ratchet effect. In addition, polarizationdependent photocurrents occur, which we interpret in terms of their underlying microscopical mechanisms. As a result, the class of ratchet systems needs to be extended by linear and circular ratchets, sensitive to linear and circular polarizations of the driving electromagnetic force.

A detailed description of the Cu-Al wire bond interface is presented, which can possibly explain the often observed corrosion failures in humidity reliability tests. Using micro-structural analysis techniques, it is shown that the unstressed interface contains up to three intermetallic phases, where the Cu-rich phases are located at the Cu-ball interface. Upon humidity stress test only the high-Cu containing intermetallic layers close to the Cu wire ball bond undergo a corrosion process, whilst the Cu-lean layers are stable in all environment stress tests. The failing layers consist out of an amorphous Al-based oxide matrix with embedded Cu precipitates. The failure process can be explained as galvanic corrosion of the intermetallic phases. The Cu-rich phases corrode faster compared to Al-rich phases, since they have an electrochemical potential lower than the Cu cathode and form, hypothetically, a less stable self-passivation oxide. The observed time-to-failure is then determined by the composition, thickness and volume of the intermetallic layers. This was verified by reliability test results performed on open wire bonds and on plastic encapsulated products. ©2010 IEEE

Vertical van der Waals heterostructures of semiconducting transition metal dichalcogenides realize moirésystems with rich correlated electron phases and moiréexciton phenomena. For material combinations with small lattice mismatch and twist angles as in MoSe 2 −WSe 2 , however, lattice reconstruction eliminates the canonical moirépattern and instead gives rise to arrays of periodically reconstructed nanoscale domains and mesoscopically extended areas of one atomic registry. Here, we elucidate the role of atomic reconstruction in MoSe 2 −WSe 2 heterostructures synthesized by chemical vapor deposition. With complementary imaging down to the atomic scale, simulations, and optical spectroscopy methods, we identify the coexistence of moire-type cores and extended moire-free regions in heterostacks with parallel and antiparallel alignment. Our work highlights the potential of chemical vapor deposition for applications requiring laterally extended heterosystems of one atomic registry or exciton-confining heterostack arrays.

This work demonstrates a large area process for atomically thin 2D semiconductors to unlock the technological upscale required for their commercial uptake. The new atomic layer deposition (ALD) and conversion technique yields large area performance uniformity and tunability. Like graphene, 2D Transition Metal Dichalcogenides (TMDCs) are prone to upscaling challenges limiting their commercial uptake. They are challenging to grow uniformly on large substrates and to transfer on alternative substrates while they often lack in large area electrical performance uniformity. The scalable ALD process of this work enables uniform growth of 2D TMDCs on large area with independent control of layer thickness, stoichiometry and crystallinity while allowing chemical free transfers to application substrates. Field effect transistors (FETs) fabricated on flexible substrates using the process present a field effect mobility of up to 55 cm2/Vs, subthreshold slope down to 80 mV/dec and on/off ratios of 107. In addition, non-volatile memory transistors using ferroelectric FETs (FeFETs) operating at ±5 V with on/off ratio of 107 and a memory window of 3.25 V are demonstrated. These FeFETs demonstrate state-of-the-art performance with multiple state switching, suitable for one-transistor non-volatile memory and for synaptic transistors revealing the applicability of the process to flexible neuromorphic applications.