The Kirkendall void (KV) has been a well-known issue for long term reliability of semiconductor interconnects. KVs exist at the interfaces of Cu and Sn and the growing intermetallic compound (IMC) Cu6Sn5 at the initial stage, and a part of the IMC is converted to Cu3Sn when the environmental stress added. In this article, all the assembled packages pass the condition of unbiased long-term reliability testing, especially for 2,000 cycles of temperature cycling test and 2,000 h of high-temperature storage. A large numbers of KVs was observed after 200 cycles of temperature cycling. Various assembly structures were monitored, and various IMC thicknesses were concluded to be functions of stress test. Cu3Sn, Ni3Sn4, and Cu6Sn5 are not significantly affected by heat, but Ni3Sn4 grows steadily.

Purpose -The Kirkendall void had been a well-known issue for long-term reliability of semiconductor interconnects; while even the KVs exist at the interfaces of Cu and Sn, it may still be able to pass the condition of unbias long-term reliability testing, especially for 2,000 cycles of temperature cycling test and 2,000 h of high temperature storage. A large number of KVs were observed after 200 cycles of temperature cycling test at the intermetallic Cu 3 Sn layer which locate between the intermetallic Cu 6 Sn 5 and Cu layers. These kinds of voids will grow proportional with the aging time at the initial stage. This paper aims to compare various IMC thickness as a function of stress test, the Cu 3 Sn and Cu 6 Sn 5 do affected seriously by heat, but Ni 3 Sn 4 is not affected by heat or moisture.Design/methodology/approach -The package is the design in the flip chip-chip scale package with bumping process and assembly. The package was put in reliability stress test that followed AEC-Q100 automotive criteria and recorded the IMC growing morphology.Findings -The Cu 6 Sn 5 intermetallic compound is the most sensitive to continuous heat which grows from 3 to 10 mm at high temperature storage 2,000 h testing, and the second is Cu 3 Sn IMC. Cu 6 Sn 5 IMC will convert to Cu 3 Sn IMC at initial stage, and then Kirkendall void will be found at the interface of Cu and Cu 3 Sn IMC, which has quality concerning issue if the void's density grows up. The first phase to form and grow into observable thickness for Ni and lead-free interface is Ni 3 Sn 4 IMC, and the thickness has little relationship to the environmental stress, as no IMC thickness variation between TCT, uHAST and HTSL stress test. The more the Sn exists, the thicker Ni 3 Sn 4 IMC will be derived from this experimental finding compare the Cu/Ni/SnAg cell and Ni/SnAg cell.Research limitations/implications -The research found that FCCSP can pass automotive criteria that follow AEC-Q100, which give the confidence for upgrading the package type with higher efficiency and complexities of the pin design.Practical implications -This result will impact to the future automotive package, how to choose the best package methodology and what is the way to do the package. The authors can understand the tolerance for the kind of flip chip package, and the bump structure is then applied for high-end technology.Originality/value -The overall three kinds of bump structures, Cu/Ni/SnAg, Cu/SnAg and Ni/SnAg, were taken into consideration, and the IMC growing morphology had been recorded. Also, the IMC had changed during the environmental stress, and KV formation was reserved.

Bumping co-planarity is a Cu pillar bump characteristic, that can impact to the joint quality of subsequent flip chip bonding process. The plated bump height variation correlates with lesser co-planarity values. Co-planarity can be minimized by bumping process, however the bumping process window is not adequate for some design features. For example, dummy bump or structure drawback features. This paper provides a methodology to improve co-planarity by collocating oval and circular bump which integrates the solder volume of different bump shapes. The final solder formation is different due to the geometry variation from the oval shape and circular shape. The final solder height can be calculated by mathematical integral from as-plated solder volume. Hence, better co-planarity can be achieved by the proposed method to collocate different bump shapes. The Cu pillar bump collocation design rules can be optimized to minimize co-planarity during initial design realization to minimize quality risks during fabrication..

Plating Solder bump is one of the key enabling technologies for flip chip assembly methodology. Flip chip assembly has advanced to support higher levels of interconnect and small feature sizes. Electroplating is a very promising technology for finer bump features when compared with solder printing and ball mounting. Hence, the plated-solder bump morphology is quite important for process quality control and design realization. This paper aims to study the plated solder behavior from as-plated mushroom structure to after reflowed bump stage photoresist sizing. In addition, this activity will consider the full bumping process integration relative to the electroplated solder bump design rules.

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