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In this paper, we present a new approach that performs timing driven placement for standard cell circuits in interaction with netlist transformations.As netlist transformations are integrated into the placement process, an accurate net delay model is available. This model provides the basis for effective netlist transformations.In contrast to previous approaches that apply netlist transformations during placement, we are not restricted to local transformations like fanout buffering or gate resizing. Instead, we exploit global dependencies between the signals in the circuit. Results for benchmark circuits show excellent placement quality. The maximum path delay is reduced up to 33 % compared to the initial timing driven placement of the original netlist and up to 18 % compared to the results obtained by consecutive optimization of the netlist and timing driven placement of the optimized netlist. This delay reduction is achieved with almost no increase in chip area. 1.

AbstTact -This paper introduces the concept of a permissible bridge and a permissible bridge pair. A bridge is a logic node with two inputs and one output. A bridge or a bridge pair are called permissible if they can be inserted into a Boolean network without changing its behavior at primary outputs. There are a total of 255 types of bridges that can be considered between any pair of wires in the network. We discuss a subset of such bridges and present three theorems related to permissible bridges for pairwise detectability, distinguishability and conditional equivalence. Experimental results show that relatively many bridges are permissible in each circuit. In this paper, we exploit the conditional equivalence of wire pairs and show that even after technology mapping, we can significantly reduce the active area as well as the wiring of many designs.

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