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MoS has received a lot of attention lately as a semiconducting channel material for electronic devices, in part due to its large band gap as compared to that of other 2D materials. Yet, the performance and reliability of these devices are still severely limited by defects which act as traps for charge carriers, causing severely reduced mobilities, hysteresis, and long-term drift. Despite their importance, these defects are only poorly understood. One fundamental problem in defect characterization is that due to the large defect concentration only the average response to bias changes can be measured. On the basis of such averaged data, a detailed analysis of their properties and identification of particular defect types are difficult. To overcome this limitation, we here characterize single defects on MoS devices by performing measurements on ultrascaled transistors (∼65 × 50 nm) which contain only a few defects. These single defects are characterized electrically at varying gate biases and temperatures. The measured currents contain random telegraph noise, which is due to the transfer of charge between the channel of the transistors and individual defects, visible only due to the large impact of a single elementary charge on the local electrostatics in these small devices. Using hidden Markov models for statistical analysis, we extract the charge capture and emission times of a number of defects. By comparing the bias-dependence of the measured capture and emission times to the prediction of theoretical models, we provide simple rules to distinguish oxide traps from adsorbates on these back-gated devices. In addition, we give simple expressions to estimate the vertical and energetic positions of the defects. Using the methods presented in this work, it is possible to locate the sources of performance and reliability limitations in 2D devices and to probe defect distributions in oxide materials with 2D channel materials.

Within the last decade, considerable efforts have been devoted to fabricating transistors utilizing 2D semiconductors. Also, small circuits consisting of a few transistors have been demonstrated, including inverters, ring oscillators, and static random access memory cells. However, for industrial applications, both time‐zero and time‐dependent variability in the performance of the transistors appear critical. While time‐zero variability is primarily related to immature processing, time‐dependent drifts are dominated by charge trapping at defects located at the channel/insulator interface and in the insulator itself, which can substantially degrade the stability of circuits. At the current state of the art, 2D transistors typically exhibit a few orders of magnitude higher trap densities than silicon devices, which considerably increases their time‐dependent variability, resulting in stability and yield issues. Here, the stability of currently available 2D electronics is carefully evaluated using circuit simulations to determine the impact of transistor‐related issues on the overall circuit performance. The results suggest that while the performance parameters of transistors based on certain material combinations are already getting close to being competitive with Si technologies, a reduction in variability and defect densities is required. Overall, the criteria for parameter variability serve as guidance for evaluating the future development of 2D technologies.

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