In recent years, extensive research has been directed toward the successful preparation of nanoscale luminescent thermometers with high sensitivities operative in a broad temperature range. To achieve this goal, we have devised a unique design and facile multistep synthesis of Zr-ctpy-NMOF@ Tb x Eu y compounds by confining Ln-complexes (Ln = Eu 3+ /Tb 3+ ) into a robust nanoscale Zr-NMOF (MOF-808) via postsynthetic modification. Covalent grafting of 4-(4′-carboxyphenyl)-2,2′:6,2″terpyridine ligand (ctpy) with a high triplet state energy and corresponding immobilization of bimetallic Ln 3+ ions resulted in yellow light-emitting Zr-ctpy-NMOF@Tb 1.66 Eu 0.14 to achieve a sensitivity of 5.2% K −1 (thermal uncertainty dT < 1 K) operative over a broad temperature range of 25−400 K. To defeat the odds related to the detection of minute temperature changes using luminescent materials, we prepared a white light-emitting Zr-ctpy-NMOF@Tb 1.4 Eu 0.31 that showed temperature-modulated multispectrum chromism where the color drastically changes from green (at 25 K, Q.Y.: 20.21%) to yellowish-green (at 200 K, Q.Y.: 23.13%) to white (at 300 K, Q.Y.: 26.4%) to orange (at 350 K, Q.Y.: 26.93%) and finally red (at 400 K, Q.Y.: 28.2%) with a high energy transfer efficiency of 49.8%, which is further supported by electron−phonon coupling.

Static random access memory (SRAM) bit cell is a prominent element for portable devices. The popularity of sleek designs and demand for longer battery life has driven memory cell into nanometer domain. This has also bolstered the need for low‐voltage devices. But reduction in operational voltage for cell is limited by process variation. In this work, a single bit line seven‐transistor (7T) SRAM bit cell is reported. The cell is designed for 32‐nm technology node and is functional at 300 mV. The reported cell maintains a 90‐mV hold and read static noise margins (SNMs), while the write margin is 190 mV. The pulse width needed to successfully write into the cell is 30 ns. The performance of proposed 7T cell is compared against different 6T, 7T, 8T, and 10T SRAM bit cells. The hold and read SNMs for proposed 7T are found to be 58.8%, better than single‐ended 6T cell, while the write ability is improved by 71.4%. The leakage current is observed to have decreased by a factor of 14 for Q = 0 (Q being the data storage node) and by factor of 28 for Q = 1, compared to 6T cell. Also, the area footprint of the proposed 7T SRAM cell is 0.442 μm2.

In this paper, a seven-transistor static random access memory (SRAM) bit cell with a single bitline architecture is proposed. This cell is designed at 32 nm and is operational at 300 mV. The static noise margin for the read and hold modes is 90 mV, while the write margin is 180 mV. Monte Carlo analysis for 6σ global variations and temperature variation analysis for temperatures in the range −10 • C to 80 • C validate its performance. The cell is compared with other single-ended 5T, 6T, 7T, 8T, 9T and 10T SRAM cells and is found to be superior in performance. As the leakage current is low, the I ON /I OFF ratio is high compared with the other cells. The power consumption of the bit cell is also found to be minimal for all modes of operation. The dynamic write analysis demonstrates that the proposed cell completes the write operation in a 10 ns pulse width. Moreover, the improvement in performance is obtained for an area as low as 0.539 µm 2 . The area of 5T, 6T, 7T-1, 7T-2, 7T-4, 7T-5, 8T, 9T and 10T cells is greater than the 7TP bit cell area by 22.

No abstract

No abstract