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Phase Change Memory (PCM) has evolved as a promising alternative over Dynamic Random Access Memory (DRAM) in terms of cell density and leakage power. While non-volatility is a desirable feature, it gives rise to the possibility of the data being present even after the power is switched off. To secure the data, encryption is normally done by using the standard Advanced Encryption Standard (AES) algorithm. Encrypting the data results in huge number of bit-flips, which reduces the lifetime of a PCM. The proposed method increases the lifetime of PCM by reducing the number of bit-flips occurred due to the encryption of modified words only and leaving the unmodified words as they are. The generated encrypted text, which is written by using the bit-flips reversal method, reduces the number of cells involved in writing by approximately 25%. This method is implemented by using Gem5 simulator and is evaluated with splash2 benchmark suite. It is observed that the proposed method improves the lifetime of a PCM memory by 15% without consuming extra power.

Emerging NVM are replacing the conventional memory technologies due to their huge cell density and low energy consumption. Restricted writes is one of the major drawbacks to adopt PCM memories in real-time environments. The non-uniform writes and process variations can damage the memory cell with intensive writes, as PCM memory cells are having restricted write endurance. To prolong the lifetime of a PCM, an extra DRAM shadow memory has been added to store the writes that comes to the PCM and to level out the wearing that occurs on the PCM. An extra address directory will store the address of data written to the DRAM and a counter is used to count the number of times the blocks are written into. Based upon the counter values, the data will be written from DRAM to the PCM. The data is written to the DRAM from the PCM, based on the data requirement. Experimental results show the reduction in overall writes in a PCM, which in turn improves the lifetime of a PCM by 5% with less hardware and power overhead.

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