Designing of Braun multipliers using various hybrid full adder circuits are described in this paper. In DSP and communication systems, multipliers are the main power consuming elements. Dynamic power dissipation contributes a lot to power consumption in CMOS logic. Braun multipliers employing Row bypassing techniques are designed to minimise the switching activities which aids in reducing dynamic power consumption. Full adders constitute a most vital part in multipliers. In this paper, Braun multiplier is designed using three different hybrid full adders .Area and power consumption of the resulting circuits are compared and analysed. The Braun multipliers are implemented and simulated using Tanner spice.