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The M • CORE microRISC architecture has been developed to address the growing need for long battery life among today's portable applications. In this paper, we present the architectural enhancements of the M3 processor, the successor to the original M • CORE M2 architecture. Specifically, we discuss the instruction buffer and pipeline enhancements, the branch prediction algorithm, branch folding for small program loops, the fast integer multiplier, and several new instructions. We present performance comparisons between the M2 and M3 M • CORE processors. Finally, we also discuss two system implementations utilizing the M • CORE M3 processor.

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Advances in technology have allowed portable electronic devices to become smaller and more complex, placing stringent power and performance requirements on the device's components. The M•CORE M3 architecture was developed specifically for these embedded applications. To address the growing need for longer battery life and higher performance, an 8-Kbyte, 4-way set-associative, unified (instruction and data) cache with programmable features was added to the M3 core. These features allow the architecture to be optimized based on the application's requirements. In this paper, we focus on the features of the M340 cache sub-system and illustrate the effect on power and performance through benchmark analysis and actual silicon measurements.