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T EST structures have played a critical role in the rapid advancement of semiconductor manufacturing technology. These structures, uniquely designed to isolate and emphasise individual artefacts of the manufacturing process, have allowed technologists to characterize and control the semiconductor manufacturing process. The International Technology Roadmap for Semiconductors identifies many of the challenges that lie ahead as technology continues to rapidly move forward. Since 1988, the International Conference on Microelectronic Test Structures (ICMTS) has provided a forum for the test structure design and user community to meet and discuss these important challenges and report on the most recent developments in this field. To this end ICMTS focuses on the design, fabrication and characterization of test structures for process and material evaluation, reliability and process failure analysis, manufacturing process control, device and circuit modeling, sensors and devices as well as associated measurement techniques and data analysis.ICMTS is one of the few international IEEE-sponsored conferences that move between Europe, Asia, and the USA in a three-year cycle. In 2003 the 16th ICMTS was held in Monterey California. Forty three papers were presented in a single track of ten sessions by authors from around the world. This special issue presents a selection of 10 papers from the meeting. Authors were asked to extend the scope of their work presented at ICMTS by adding the latest developments on the progress of their chosen field of study to their paper presented in this special issue.Papers were selected based upon the merit of the work and to demonstrate the broad spectrum of test structure design and use by a world-wide community. Papers presented report on materials manufacturing topics such as an advancement in critical dimension calibration standards, refinements to the Greek cross for sheet resistivity estimation, and the monitoring of the depth of deep trenches. To accelerate yield enhancement and reduce process variation four papers propose novel large-scale test structures. Device performance is optimized for RF varactors and the problem of characterising effective oxide thickness for sub-100-nm technologies is evaluated and the negative bias temperature instability locally characterized. Finally, new materials for future low cost manufacturing methods are introduced with a paper on photosensitive organometallic materials for MOS processes. For those with further interest in microelectronic test structures the ICMTS conference proceedings contains the complete set of papers presented in Monterey and is available from the IEEE.We would both like to take this opportunity to thank the authors for their efforts in the preparation of the manuscripts and keeping to the deadlines that were set by the editorial requirements. We are also very grateful to the reviewers who both refereed the manuscripts in a timely manner and provided helpful and valuable feedback to the authors. We would also like to express our gr...

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