Mycoherbicides are exclusive biotechnology products which offer a non-chemical solution to control noxious weeds on the land as well as aquatic in systems, viz a viz saving environment from hazardous impact of synthetic chemicals. The present paper highlights the mycobiota associated with Eichhornia crassipes infesting Harike wetland area of Punjab and evaluation of their pathogenic potential for futuristic application as a mycoherbicide. Of the 20 isolates tested by leaf detached assay and whole plant bioassays, only one isolate (#8 BJSSL) caused 100% damage to E. crassipes. Further, the culture filtrate of this isolate also exhibited a similar damage to the leaves in an in vitro detached leaf assay. The potential isolate was identified as Phaeoacremonium italicum using classical and modern molecular methods. This is the first report of P. italicum as a pathogen of E. crassipes and of its potential use as a biological control agent for the management of water hyacinth.

In This paper we discuss the glitch and hazard power compensation techniques which involves reducing the undesired switching of combinational circuits in order to save the dynamic power for CMOS stander cell designs in 90nm. In nanometer CMOS technologies the power consumption is become a serious concern. The total power consumption is mainly due to the dynamic and leakage power consumptions. In CMOS circuits a glitch occurs when differential delay at the inputs of a gate is greater than inertial delay, which gives an amount of power consumption. In lower technology nodes this glitch power is a major prominent. Experimental results gives 12% to 50% reduction in top 10 peak undesired transition. The proposed methodology has been validated using cadence 90nm gpdk technology libraries.

In this paper work, a new XOR logic gate and multiplexer logic has been proposed. Proposed design shows acceptable output logic levels with noise margin of 0.5V with 1.0V as input signals in 45nm technology. A full adder design for single bit has been implemented using proposed XOR gate, pass transistor logic multiplexer. The full adder designed with 12 transistors shows power dissipation of 7.74nW and maximum output delay 59.74nS. This circuit works with well reduced supply and simulations have been carried out for 0.8V, 1.0V & 1.2V supply voltage in the step of 0.2V. Simulations are performed by using CADENCE based on gpdk45 library CMOS technology. Simulation result provides the advantage of the newly designed adder circuit against the conventional adder circuits. Consumption of power for proposed full adder has been compared with earlier reported full adder circuits, this proposed design circuit gives better performance in terms of power consumption, speed and transistor count.

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