Since the mechanisms of an operating system can significantly affect the performance of parallel programs, it is important to customize operating system functionality for specific application programs. In this paper, we first present a model for adaptive objects and the associated mechanisms, then we use this model to implement adaptive locks for multiprocessors which adapt themselves according to user-provided adaptation policies to suit changing application locking patterns. Using a parallel branch and'bound program, we demonstrate the performance advantage of adaptive locks over ezisting locks.

Recently, lightweight thread libraries have become a common entity to support concurrent programming on shared memory multiprocessors. However, the disparity between primitives offered by operating systems creates a challenge for those who wish to create portable lightweight thread packages. What should be the interface between the machine-independent and machine-dependent parts of the thread library? We have implemented a portable lightweight thread library on top of Unix on a KSR-1 supercomputer, BBN Butterfly multiprocessor, SGI multiprocessor, Sequent multiprocessor and Sun 3/4 family of uniprocessors. This paper first compares the nature and performance of the OS primitives offered by these machines. We then present procedure-level abstraction that is efficiently implementable on all the architectures and is a sufficient base upon which a user-level thread package can be built.

No abstract

X `Y ba bc ed gf ih bp qp sr th 6u ¨v xw ic y by y V V "d e gf i g h f i ei kj l Eh m nf np oy p rq ts uc "r vh mp r w n g "x yd z V "d e gf i g h f i ei kjg kd z ¨ ¢w g Uw vd mz k g U ge g© xf w i hª ` x vf © «f b¬ gf i nf z ee y f w f id m g ¨w ¨ x yw e kd me ve g f Vd me e nd gz Uf z "e § h g x f o § « g d mz k nf t § x vd ®© «d g gf e £ E m § d nd ¡ g¡ gf ¡ kd ¡ g °d me g «z ¨w d b ± gf i² xi g f 6e f 6d b© «d g¡ d g¡ g ge £ E m § ³© «d m d z ee gw y § f n¦ gw e gz g ¢e g g© «f w t « ®d « e ge g ¢ xz kd ¡ I¡ g x t£¡ gf © «f ¡ f i g kd z gw g Uw i z f ¨d ¨ ed « g We g ´w g «¡ g© «f e gw x ¡ gf µ gw Ee g ´ m¤ tf Ud ¨¡ g g « ee £x tf g « ee i¬ ¶ gf i n «z ¥ k «i nd ¡ gf d mz k f n¦ e f z ¨w g ¡ gf ± f d me gz ¨w g ew e f • xf z ¨f ¡ £ Uz ¹d ¡ g d e g ¢ xz ´ rd b n xz e¥ k xi f ¢e ®e g w gi ge ge w z ¨f f i ew b¬ gz k n¡ gi k ¢z ¨ e g f ±w f ¡ ¢f b ne g «z 8 m § ºd ¨ d e gf ±¡ g x ts¡ gf © xf ¡ «¡ g n gf w i¬ e ¨f U n «z w ge gi k ne g xz 8 § vz f x g U ge g© xf w xz 8e m § e f f n¦ gw e gz » «z f w $ « 6e f ±f n¦ e gf z w g xz Wx y ge Wd x e ge g «z d ¡ g ¢e g g© «f w b U¼ £z 8e g gw d f b¬ ¶x vf gz e© «f w ge g "d me f r «f z f ¡ ® n «z ¥ k «i nd g¡ g ge £ ¹d mz k Pf n¦ e f z ¨w g g¡ g ¢e £ § q « ±d w f i n °¥ t ¨ n¡ d mw w ± § ® f d me gz 8w g "w ge f g g U ge g© «f w i½ e xw f i w gf i § x ve nd w g U « ye g f bd « rw g "z ¨ «z ¨ ¢¾ bd e g xz h ¶¿ 8f f w gf z ee d z r g ¡ gf ±f z ee nd e g xz E m § ±i ¡ ge g nf w gw « À¡ ¢ g ew e d e v d mz U f gf i n «z ¥ k «i gf i ±w ge d me d ¡ g¡ g ±d z k ± e ez kd m U d m¡ ¢¡ g « ¼ £z Ud x e ge g «z ¬ x vf f n© xf ¡ g d $ f f w gf z ee d me g «z r § q « te f ®¡ g Ud m w e g d x ne g «z rd z k d z rd w w g n d e f b U gf i n xz e¥ k «i ¨ d e g g «z r Uf i g kd mz gw e g kd e t d b 6 kf i w f b ± § q « te f ® ef © «f ¡ ¢ Uf z "e t § h xe f n «z e¥ «i nd ¡ gf Vd mz k ±f u¦ e gf z w g ¢ ¨¡ ¢f ® f nd e g ¢z ¨ Ew g "w ge f d m w e g d « ue g «z w b Á «¡ g¡ gf xf § Á « i e gz  f « g « d $¼ £z w e g ¢e gi e f $ § à ¶f i g z ¨ «¡ g « x ye g¡ d z ee d ¨¬  f « g « d ÅÄ xAE «Ä xÄ «Ç bÈ AE «Ç xÉ «AE

Blocking locks are commonly used in parallel programs to improve application performance and system throughput. However; most implementations of such locks su[fer.from two major pmhlems -latency and scalability In this paper; we pmpose an implementation of blocking locks using scheduler adaptation which exploits the interaction between thread schedulers and locks. By experimentation using wellknown multiyrocessor. applications on a KSR2 multipi-ocessor; we demonstrate how such an implementation considerably reduces the latency and improves the scalability of blocking locks.