Hotspots on a microelectronic package can severely hurt the performance and long-term reliability of the chip. Thermoelectric coolers (TECs) can provide site-specific and on-demand cooling of hot spots in microprocessors. We develop a 3D compact model for fast and accurate modeling of a TEC device integrated inside an electronic package. A 1D compact model of a TEC is first built in SPICE and validated for steady-state and transient behavior against a finite-volume model. The 1D compact model of the TEC is then incorporated into a 3D compact model of a prototype electronic package. The results from the compact model for the packaged TEC are in good agreement with a finite-volume based model, which confirms the compact model's ability to accurately model the TEC's interaction with the package. Analysis of packaged TECs using this 3D compact model shows that (i) moving TECs closer to the chip results in faster response time and an increase in maximum cooling, (ii) high thermal contact resistance within the thermoelectric cooler significantly degrades performance of the device, and (iii) higher convective heat transfer coefficients (HTC) at the heat spreader surface increase steady-state cooling but decrease maximum transient cooling.

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A configurable, channel-adaptive K-best multipleinput, multiple-output (MIMO) detector for multi-mode wireless communications that adapts computation to varying channel conditions to achieve high energy-efficiency is presented. An 8-stage configurable MIMO detector supporting up to a 4 × 4 MIMO array and BPSK to 16-QAM modulation schemes has been implemented and simulated in 0.80 V, 22 nm Tri-gate CMOS process. Dynamic clock gating and power gating enable on-the-fly configuration and adaptive tuning of search radius K to channel response which results in 10 to 51 % energy-efficiency improvement over nonadaptive K-best MIMO detectors. During unfavorable channel conditions, the MIMO detector satisfies target bit error rate (BER) by setting K = 5. For favorable channel conditions, K is reduced to 1, where 22 nm circuit simulations show 68 % energy reduction. At 1.0GHz target frequency, the total power consumption is 15 mW (K = 1) to 35 mW (K = 5), resulting in energy-efficiency of 14.2pJ/bit (K = 1) to 44.7pJ/bit (K = 5) and 3.2Gbps throughput.

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Hot spots on a microelectronic package can severely hurt the performance and long-term reliability of the chip. Thermoelectric coolers (TECs) have been shown to potentially provide efficient site-specific on-demand cooling of hot spots in microprocessors. TECs could lengthen the amount of time a processor is capable of running at full speed in the short-term and also provide long-term reliability by creating a more uniform temperature distribution across the chip. We have created a compact model for fast and accurate modeling of the TEC device integrated inside an electronic package. A 1-D compact model for TEC is first built in SPICE and has been validated for steady-state and transient behavior against a finite-volume model. The 1-D model of TEC was then incorporated into compact model of a prototype electronic package and simulations were performed to validate its steady state and transient behavior. This integrated compact model’s results are in good agreement with a finite volume based model developed for TECs integrated inside a package and confirmed the compact model’s ability to accurately model the TEC’s interaction with package. The compact model has relatively small error when compared to the finite-volume based model and obtains results in a fraction of the time, reducing run-time in a transient simulation by 430%. A simple controller was added to the electronic package and TEC model to provide an initial test of how the compact model can aid design of more complex control systems to efficiently operate the thermoelectric coolers.