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This research considers the offloading of the IPsec packet encryption algorithm into an FPGA by proposing a hardware acceleration of the AES cryptographic algorithm for IPsec. We point out the benefits of relying on HW acceleration in terms of speed and energy efficiency for applications like IPsec. We present the description of the architecture of the proposed solution, the simulation results of our implementation of the AES algorithm in ECB (Electronic Code Book) mode. We also present the integration of the encryption core with the IPsec subsystem through a PCIe bus interface so that the resulting implementation is interoperable with other systems.

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The aim of the present work is the hardware implementation of the elliptic curve Diffie-Hellman (ECDH) key exchange protocol on a reconfigurable circuit of type FPGA at the register-transfer level (RTL). Compared to the standard Diffie- Hellman (DH), based on exponentiation in a finite field, ECDH is known to provide equivalent level of security with lower number of bits used. Reduced bit usage implies less power and logic area are required to implement this cryptographic scheme. This is particularly important in secure embedded system, where a high level of security is required, but with low power consumption. The results show that ECDH can be implemented on FPGA with convincing performances in comparison with other published works