A Multi Logic Memory cell have various logic between one and zero that's why fuzzy logic is also known as multiplelogic level, when the paper work was in plan originally plan was do something in Fuzzy Electronics. Lots of fuzzy systems is been developed already but from observing fuzzy flip-flops working the idea comes for the proposed work. Paper work propose designs of a new fuzzy memory cell(flip-flop) for four logic levels which can hold Logic 0, Logic 1, Logic 2 & Logic 3 total four fix logic .though fuzzy logic deals with approximate logic rather than fix proposed work has fix logic and it is the big difference between proposed work and fuzzy based memory cell. Proposed work also has design an Interfacing module between fuzzy memory with Digital) systems, just for make proposed four logic flip-flop compatible with existing binary logic based digital system application for proposed design that one can reduce the no. of wires required when to establish parallel interface with memory and also one can increase the speed or throughput of simple serial data transfer.

Image mosaicing algorithm based on random corner method is proposed. An image mosaicing is a method of combining multiple photographic with overlapping fields of view to produce a segmented panorama of high resolution image. The output of image mosaic will be the combination of two input images. In this paper we are using three step image mosaic methods. The first step is taking two input images and finding out the corners in both the images, second step is removing out the false corner in both the images and then by using homography we find its matched corner pair and we get final output mosaic. The experimental results show the proposed algorithm produces an improvement in mosaic accuracy, efficiency and robustness.

In this paper we demonstrate an efficient and compact reconfigurable hardware implementation of the Data Encryption Standard (DES) algorithm. Our design was implemented on FPGA of device VirtexEXCV400e. As a strategy to reduce the associated design critical path, we utilized a parallel structure that allowed us to compute all the eight DES S-boxes simultaneously. The testing of theimplemented design shows that it is possible to generate data in 16 clock cycles when non-pipelined approach is employed. Whenpipelined approach is employed on the other hand, 17 clocksignals are required for the initial phase only, and one clocksignal is sufficient afterwards for each data generation cycle. TheVery High Speed Integrated Circuit Hardware DescriptionLanguage (VHDL) is used to program the design.

A adder is one of the key hardware blocks in most digital and high performance systems such as FIR filters, digital signal processors and microprocessors etc. With advances in technology, many researchers have tried and are trying to design many types of adder such as ripple carry adder, carry skip adder, carry a look head adder and carry select adder. Among this adder carry select adder is the high speed, low power consumption and hence less area or even combination of them in adder. However area and speed are two conflicting constraints.

In modern days data transmission through a channel requires more security. Security based more important transmission is comparatively better & believable than simple transmission. The aim of this work to use RC5 algorithm for encryption and decryption of data for secure data transmission from one place to another place for proper communication purposes. Today this is utmost importance to send information confidentially through network without any risk for hackers or unauthorized possibility to access from the network. This urgently require security implementation devices in network for well secured transmission of data. Symmetric encryption cores provide data protection through the use of secret key only known as encryption, whereas decryption deals with the yield at the end of communication path. Today world require secure transmission through cryptographic algorithm. Keeping view in mind the proposed well defined RC5 architecture have been taken, based on the fact for suitability of each operation for encryption, high speed processing and possibility of area reduction. The work results of the study clearly indicate that logic implementation by this hardware is maximum clock frequency of 179 MHz and areas reduced to 50% as compare with the results of design of previous worker. The propose design is described in verilog, synthesized by Xilinx synthesis technology.