No abstract

In this work, the influence of proton-irradiation in the voltage gain of two-stage operational transconductance amplifier (OTA) designed with silicon-on-insulator (SOI) fin field effect transistors (FinFETs) is studied. The OTA simulations were performed using Verilog-A approach based on experimental data extracted from the SOI FinFET electrical characterization, before and after proton-irradiation. The OTA is designed with SOI FinFETs of fin widths (W fin) of 20 nm, 120 nm, and 870 nm, all in the same predefined inversion region (g m/I D = 8 V−1). All evaluated OTA circuits exposed to proton-irradiation presented a voltage gain increase (compared with pre-irradiation circuits), of 0.87 dB, 1.19 dB, and 6.16 dB for fin widths of 20 nm, 120 nm, and 870 nm, respectively. The results show that despite the typical radiation effect of degradation of the individual transistors (it being more severe for larger fin width SOI FinFET), these effects combined in OTA circuits result in an unexpected improvement in DC voltage gain, especially for wider fins. Focusing on the fin width impact on the OTA voltage gain, before and after proton-irradiation, it is much greater for narrow fin width SOI FinFET thanks to the better Early voltage.

In this work, a simple methodology is proposed to simulate the current mirror circuit based on the triple-gate SOI FinFET experimental data, called lookup table in Verilog-A. It was analyzed the reliability of the model, comparing between experimental and simulated data, with has proven to be reliable. It was also evaluated the performance of the transistor and as well the circuit regarding the efficiency and the gain, for p- and n-types, based on three different fin widths, before and after proton-irradiation.

Neste trabalho é proposto o projeto de um amplificador operacional de transcondutância (OTA) com transistores SOI FinFETs e o estudo do efeito da radiação ionizante de prótons sobre tais circuitos. Uma vez que o SOI FinFET não tem um modelo analítico-matemático de primeira ordem preciso para programas de simulação elétrica, é proposto o uso do método chamado 'lookup table' em Verilog-A.Esse método consiste na caracterização experimental detalhada do dispositivo SOI FinFET para obtenção do seu comportamento elétrico para alimentar uma tabela com os dados e simular suas interpolações, que serão utilizados em simulações de circuitos. Utilizando este método, os dispositivos FinFET dos tipos p e n com três diferentes larguras de aleta (Wfin) foram analisados (20 nm, 120 nm e 870 nm) e utilizados tanto em circuitos básicos (como o circuito de polarização intitulado também de "bias" e o espelho de corrente) como em circuitos amplificadores operacionais de transcondutância de dois estágios (Operational Transconductance Amplifiers -OTA).Apesar da conhecida degradação causada pela radiação ionizante nos dispositivos semicondutores, e no caso dos FinFETs naqueles dispositivos que possuem maior largura de aleta, a combinação dos efeitos causados nos dispositivos que formam o OTA resulta num inesperado aumento de ganho de tensão em todos os circuitos estudados. No caso do OTA estudado, observou-se um aumento de ganho de tensão diferencial quando comparados os circuitos pré-radiados e pós-radiados, para todos os circuitos estudados. Este aumento de ganho de tensão foi de 1,84 dB, 2,38 dB e 6,16 dB, para os circuitos OTA formados por dispositivos FinFETs de Wfin de 20 nm, 120 nm e 870 nm, respectivamente. Já no caso dos OTAs com fonte de corrente ideal, os resultados de aumento de ganho tensão obtidos foram de 0,87 dB, 1,19 dB e 6,21 dB, para os circuitos formados por dispositivos FinFETs de Wfin de 20 nm, 120 nm e 870 nm, respectivamente. Estes aumentos de ganhos de tensão nos circuitos pósradiados estão relacionados à mudança dos pontos de polarização nos circuitos, que causa diferentes valores de transcondutância (gm) e condutância de saída (gD). Essa variação na condutância de saída é mais relevante no dispositivo pFinFET, principal responsável pelo aumento do ganho de tensão após a radiação.Palavras-chave: radiação de prótons, SOI FinFETs, lookup table, Verilog-A, circuitos analógicos.

In this work, a simple methodology is proposed to simulate the current mirror circuit based on the triple-gate SOI FinFET experimental data, before and after proton-irradiation. The method is called lookup table in Verilog-A, consisting of a detailed experimental characterization of the device aiming the construction of lookup table with the data to be used in simulations, once the device do not have an accurate first order analytic model (1-4). Even though the SOI technology provides significant immunity to single-event phenomena when compared to bulk transistors, the radiation effect still have to be considered because the trapped charges in the buried oxide (BOX) degrades the transistor characteristics due to the higher Total Ionization Dose (TID) (5-9). The studied devices are p- and n-type triple-gate SOI FinFETs fabricated in imec, Belgium. They were processed on SOI substrates with a thick buried oxide (tBOX) of 150 nm. The gate dielectric of the devices consists of 2 nm HfSiON on 1 nm SiO2 interfacial layer, resulting in an Equivalent Oxide Thickness (EOT) of 1.5 nm. The gate is 10 nm TiN covered by 100 nm poli-Si. The fin height (hFIN) is 65 nm, the channel length (L) is 150 nm and three different fin widths (WFIN) were evaluated: 20 nm, 120 nm and 870 nm. Each transistor has 5 fins in parallel. The proton irradiation has been performed at the Cyclone facility in Louvain-la-Neuve (Belgium) with the beam energy of 60 MeV up to fluence of 1012 p/cm2. Figure 1 shows the experimental drain current (IDS) as a function of the front gate voltage (VGF) for different fin widths before and after the radiation. It is possible to notice that although narrow devices (WFIN=20nm) showed to be almost immune to proton irradiation due to a higher coupling between gates, the wider devices presents a degradation on subthreshold swing (SS) for n-FinFETs while for p-FinFET the SS improves. The reason is that the radiation induces positive charges in the buried oxide, resulting in a reduction of the threshold voltage at the back interface (Vth2), which is good for p-FinFET and bad for n-FinFET, as explained in (8-10), Figure 2 shows the drain current (IDS) as a function of the drain voltage (VDS) for different fin widths before and after the radiation, for simulated and experimental data. It shows that the simulation values accurately fit the experimental data. Some important figures-of-merit of analog performance for circuit applications should also be evaluated, such as transistor efficiency (gm/IDS) and the intrinsic voltage gain (Av). Figure 3 shows that the n-FinFETs presents a degradation of the transistor efficiency (except for narrow fin) after radiation since the weak inversion region is inversely proportional to SS. For p-FinFETs after radiation, the opposite behavior of gm/IDS was obtained once SS improves. At the strong inversion region, there is only a slightly variation of the transistor efficiency due to mobility degradation. From figure 4 it is possible to observe that the radiation causes an improvement of intrinsic voltage gain (Av = gm/IDS x VEA) for p-FinFETs and a degradation for n-FinFETs, for all inversion conditions, following the gm/IDS tendency. It is also expected that narrow devices present higher gain due to the higher VEA, caused by the better coupling between gates, for both types of transistor. The evaluated current mirror circuit regarding the behavior with different loads (VLOAD) is schematic represented in Figure 5. Figure 6 presents the relation between drain currents (ILOAD/IREF) as a function of the VLOAD before and after the circuit be submitted to proton irradiation. For this analysis, the perfect matching situation, i.e. drain current ratio of 1, was obtained for |VGS=1V| for both devices types before radiation. From the insets of figure 6 it is possible to visualize that after radiation, the perfect matching situation presents a slightly variation and is obtained for a more negative VGS bias, for both types, due to the threshold voltage (VT) change (promoted by the Vth2 reduction). In addition, from figure 6 it can also be noticed the influence of VEA on VLOAD at the operation region of the current mirror, which results in a maximum current variation smaller than 10 percent, even for radiated current mirrors. Beside the matching situation, it is also possible to notice that narrow transistors present a higher compliance voltage even for radiated devices due to the better coupling between gates and consequently the immunity to the buried oxide charges. Figure 1