For double fields and large code lengths, Low-Density Parity-Check (LDPC) code approaches Shannon-limit execution. The goal of this project is to present an LDPC calculation for Min Sum (MS) decoding and equipment execution inquiry within a communication framework that has been proposed. The MS calculation principally utilizes the base and expansion finding procedure. The quantity of increases is subsequently altogether diminished, which tends to decrease the execution intricacy. The consequences of the reenactment show that the proposed MS interpreting calculation performs the same as the translating of the Sum-Product Algorithm (SPA) while keeping up with the principle highlights of the MS disentangling. The further developing execution by diminishing the number of stages in the deciphering system, diminishing the intricacy of the implementation of the Field Programmable Gate Array (FPGA).