A new sustain driving method is proposed to improve luminous efficiency by the generation of the self-erasing discharge during a sustain period in AC plasma display panel. As one subfield time in the conventional AC PDP is divided into the reset, address, and sustain period. Among them, as the square sustain waveform is alternately applied to the X and Y electrodes on the front plate during the sustain period, the plasma discharge for displaying the image is continuously produced. Meanwhile, in the conventional driving method, the address waveform applied to the A electrode on the rear plate is only driving during an address period and grounded during a sustain period. In this experiment, the negative pulse is applied to the A electrode at the latter part of the sustain pulse for improving the luminous efficiency producing the self-erasing discharge during the sustain period. The negative pulse on the A electrode can change from the space to the wall charge and induce the additional discharge by the accumulated wall charge when the voltages of three electrodes are grounded. As a result, the luminous efficiency will be measured with changes in the voltage level of the A electrode and the new driving method can be improved to the luminous efficiency about 32 % compared with the conventional driving method.

The address discharge time lags are investigated in each subfield time in AC plasma display panel and a modified driving waveform is proposed to reduce the address discharge time lag by applying different additional scan voltage under no misfiring discharge production. The weak plasma discharge in AC PDP is generated by applying high positive-going ramp waveform to the scan electrode during the first reset period and that induce the production of the priming particle and wall charge. Because the wall charge becomes the wall voltage in a cell, the wall plus external address voltage produce the address discharge. However, as the wall charge in a cell is gradually disappeared as time passed, the address discharge time in the subfield time for 1 TV frame is lagged. In the first subfield time, the address discharge is faster produced than the other subfield time because the wall charge are much remained by the high positive-going ramp voltage during the reset period in the first subfield time. Meanwhile, from the second to last subfield, the address discharge production time is gradually delayed due to the dissipation of the wall charge in a cell. In this study, the address discharge time lags are measured in each subfield time and the total address discharge time lags are shortened by applying the different additional scan voltage during the address period in each the subfield time.