Three-dimensional-integrated circuits (3D-ICs) bring new issues for power delivery network design because of larger current density and more complicated power delivery paths compared to 2D-IC. The power delivery network consists of power bumps, through-silicon-vias (TSVs), and power wires. IR-drop at each node varies with the number and position of power bumps and TSVs. These three power resources affect IR-drop of 3D-ICs. In this study, the authors propose power delivery network design methodology to optimise power resources wherease IR-drop constraint is satisfied. The simulation results show that the proposed method minimises the number of power bumps and TSVs compared to the conventional method.

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Abstract-Higher integrated density in 3D ICs also brings the difficulties of routing, which can cause the routing failure or re-design from beginning. Hence, precise congestion estimation at the early physical design stage such as floorplan is beneficial to reduce the total design time cost. In this paper, an effective estimation method of routing congestion is proposed for 3D ICs at floorplan stage. This method uses synthesized virtual signal nets, power/ground network and clock network to achieve the estimation. During the synthesis, the TSV location is also under consideration. The experiments indicate that our proposed method had small difference with the estimation result got at the post-placement stage. Furthermore, the comparison of congestion maps obtained with our method and global router demonstrates that our estimation method is able to predict the congestion hot spots accurately.

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