Abstract:In this paper, novel explicit pulse-based flip-flop having dual precharge nodes is presented. Dual precharging can minimize the parasitic capacitance of each precharge node by making output transistors driven separately, resulting in high-speed and low-power operation. The switching speed is further improved by avoiding the use of stacked transistors for driving the output load. Pulse-based nature of the proposed flip-flop also provides a negative setup time and minimizes the effects of clock skew. The proposed flip-flop was designed using a 0.18 um CMOS technology, whose comparison results indicate that the flip-flop achieves up to 32% power reduction with 11% speed improvement. They also indicate that the power-delay product is decreased by up to 39% compared to conventional pulse-based flipflops. Keywords: dual precharging, pulsed flip-flop, low power, high speed Classification: Integrated circuits References[1] V. Stojanovic and V. G. Oklobdzija, "Comparative analysis of masterslave and flip-flops for high-performance and low-power systems," IEEE J. Solid-State Circuits, vol. 34, no. 4, pp. 536-540, April 1999. Solid-State Circuits, vol. 34, no. 5, pp. 712-716, May 1999. [4] J. Tschanz, S. Narendra, S. Zhanping Chen Borkar, and M. Vivek De Sachdev, "Comparative delay and energy of single edge-triggered and dual edge-triggered pulsed flip-flops for high-performance microprocessors,"

This paper describes novel bootstrapped CMOS logic family operating at ultra-low supply voltages. The proposed logic family provides better switching performance than conventional bootstrapped logic family by isolating the bootstrapping circuit from timing-critical signal paths. The logic family also minimizes area overhead due to the bootstrapping circuit by adapting a differential structure having a single bootstrap capacitor shared between complementary outputs. Multi-input XOR/XNOR gates and 64-bit adders were designed in 0.18 um CMOS process as test vehicles for assessing the performance. Comparison results indicate that the power-delay product of the proposed logic family is improved by up to 67% compared to conventional differential logic circuits at the supply voltage ranging from 0.5 V to 0.8 V. Solid-State Circuits, vol. sc-17, no. 3, pp. 614-619, June 1982. [4] J. H. Lou and J. B. Kuo, "A 1.5 V full-swing bootstrapped CMOS large capacitive-load driver circuit suitable for low-voltage CMOS VLSI," IEEE J. Solid-State Circuits, vol. 32, no. 1, pp. 119-121, Jan. 1997. [5] J. H. Lou and J. B. Kuo, "A 1.5-V CMOS all-N-logic true-single-phase bootstrapped dynamic-logic circuit suitable for low supply voltage and high-speed pipelined system operation," IEEE Trans.