The key process steps for growing high-quality Si-based epitaxial films via reduced pressure chemical vapor deposition (RPCVD) are investigated herein. The quality of the epitaxial films is largely affected by the following steps in the epitaxy process: ex-situ cleaning, in-situ bake, and loading conditions such as the temperature and gaseous environment. With respect to ex-situ cleaning, dry cleaning is found to be more effective than wet cleaning in 1:200 dilute hydrofluoric acid (DHF), while wet cleaning in 1:30 DHF is the least effective. However, the best results of all are obtained via a combination of wet and dry cleaning. With respect to in-situ hydrogen bake in the presence of H2 gas, the level of impurities is gradually decreased as the temperature increases from 700 °C to a maximum of 850 °C, at which no peaks of O and F are observed. Further, the addition of a hydrogen chloride (HCl) bake step after the H2 bake results in effective in-situ bake even at temperatures as low as 700 °C. In addition, the effects of temperature and environment (vacuum or gas) at the time of loading the wafers into the process chamber are compared. Better quality epitaxial films are obtained when the samples are loaded into the process chamber at low temperature in a gaseous environment. These results indicate that the epitaxial conditions must be carefully tuned and controlled in order to achieve high-quality epitaxial growth.

The p-type nanowire field-effect transistor (FET) with a SiGe shell channel on a Si core is optimally designed and characterized using in-depth technology computeraided design (TCAD) with quantum models for sub-10-nm advanced logic technology. SiGe is adopted as the material for the ultrathin shell channel owing to its two primary merits of high hole mobility and strong Si compatibility. The SiGe shell can effectively confine the hole because of the large valence-band offset (VBO) between the Si core and the SiGe channel arranged in the radial direction. The proposed device is optimized in terms of the Ge shell channel thickness, Ge fraction in the SiGe channel, and the channel length (L g ) by examining a set of primary DC and AC parameters. The cutoff frequency (f T ) and maximum oscillation frequency (f max ) of the proposed device were determined to be 440.0 and 753.9 GHz when L g is 5 nm, respectively, with an intrinsic delay time (τ) of 3.14 ps. The proposed SiGe-shell channel p-type nanowire FET has demonstrated a strong potential for low-power and high-speed applications in 10-nm-and-beyond complementary metal-oxide-semiconductor (CMOS) technology. K E Y W O R D SCMOS technology, high hole mobility, low-power high-speed operation, nanowire FET, SiGe shell channel, sub-10-nm logic technology, valence-band offset . His current research interests include nanoscale CMOS devices, emerging memory devices and array, photonic devices and integrated circuits, and neuromorphic systems.