No abstract

The System 75 office communication system uses a unique communications and control architecture that provides great flexibility and a minimum of overhead for small configurations while growing smoothly to larger line sizes. A distributed communication network provides 64 kb/s connectivity for both voice and data. It consists of a pair of time division multiplexed buses and intelligent port circuits. Flexible conferencing and gain adjustment are supported as an integral part of the network. The control complex supports an operating‐system‐based software structure.

Implementation of the Transaction Network required development of new equipment and integration of existing equipment to create a message switch and a communication network that interfaces with the switch by means of polled, dial, and synchronous access. Particular emphasis was placed on the reliability and maintainability of the system. I. MESSAGE SWITCH COMMON EQUIPMENTThe central element of the Transaction Network is the message switch. Besides providing termination for polled, dial, and synchronous com munication facilities, the message switch controls and routes traffic, performs the billing and administration function, and controls main tenance of the network. 1 2The configuration of the common equipment is shown in Fig. 1. The arrangement was designed with particular emphasis on reliability and maintainability. Much of the equipment is also used in systems other than the Transaction Network. ProcessorThe Auxiliary 3A Processor is an enhanced version of the same pro cessor used in the No. 2B and No. 3 E S S systems. 3 The principal en hancements consist of the addition of parallel input-output channels, direct memory access capability, and microprogrammed instructions that are useful in applications other than line switching.The processor is a duplicated unit, containing two 3A central controls and two semiconductor memories. In the initial Transaction Network installations, 256K words are required in each memory, each word con sisting of 18 bits including two parity bits. A t any time, one processor 3349 THE BELL SYSTEM TECHNICAL JOURNAL, DECEMBER 1978and memory are active. The standby memory is continually updated so that the standby processor may be switched on line, with minimum disruption of service, in case of a fault in the active system, including an input-output port.A maintenance frame associated with the duplicated processor in cludes a system status panel, two cartridge tape units used for loading programs, a teletypewriter, two teletypewriter control units which may serve several remote teletypewriters as well as the local one, and relays for activating office alarms. All these peripherals are connected to the processor via serial channels.Parallel channels are used between the processor and the various communication ports to effect fast data transfer. Each processor contains a main parallel channel which couples to several subparallel channels. At each peripheral device, a duplex bus selector ( D B S ) is connected to a parallel channel from each processor. Under processor control, the D B S switches communication from the device to the active channel. The D B S insures that no single processor or channel failure will render the device inoperative, and also prevents any device failure from disabling the channel. Each pair of subparallel channels can support a chain of 16 D B S s and their associated devices.