No abstract

Grooved gate metal-oxide-semiconductor field-effect transistors (MOSFETs) are known to alleviate many of the short channel and hot carrier effects that arise when MOSFET devices are scaled down to very short channel lengths. However, they exhibit much higher parasitic capacitance with stronger bias dependence when compared to conventional planar devices. In this paper, we present a model for gate-to-drain and gate-to-source capacitance characteristics of a deep submicrometre grooved gate MOSFET. Both the intrinsic and extrinsic parts of the capacitance are modelled separately. In particular, the model presents a novel but simple way to account for the accumulation layer formation in the source/drain region of MOSFETs due to the application of the gate voltage. The results are compared with those obtained from a two-dimensional device simulator. The close match between the modelled and simulated data establishes the validity of the model. The model is then used to account for the superiority of capacitance characteristics of planar device structures and to arrive at optimization guidelines for grooved gate devices to match these characteristics.

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Charge collector damage, caused by process-induced charging of thin gate oxide capacitors, is a crucial yield and reliability limiter for submicron technology. Wafer level testing on a unique set of test structures shows that charge collector ratios of exposed and buried conductive collectors is important in determining the amount of degradation. Various equipment and processes such as resist strip, plasma etch, sputtering, and ion implantation are evaluated and improvements made to create a robust fabrication environment. A new model, incorporating the charge-sharing model and the new "charge strike" defect density model, is used to explain how charge collector damage occurs and is evaluated vs.

No abstract