This paper presents a novel 8T SRAM cell which contains two tail transistors in the pull-down path of the respective inverter to minimize the write power consumption. The simulated results show that the proposed cell consumes about 57.87% lower power and gives faster response compared to the conventional 6T SRAM cell during a write operation. To compensate the read delay and static noise margin (SNM) losses due to the two extra tail transistors in the proposed cell, we have to enlarge the width of these two tail transistors.

Power consumption and Static noise margin (SNM) are most important parameters for memory design. The main source of power consumption in SRAM cell is due to large voltage swing on the bitlines during write operation. To reduce the power consumption and enhance the performance of the SRAM cell, we propose a Low-power fast (LPF) SRAM cell. The cell is simulated in terms of power, delay and read stability. The simulated result shows that the read and write power of the proposed cell is reduced up to 33% and 57.12% at 1.2 V (in CMOS 0.12 µm technology) respectively compared to the 6 T cell. The read SNM of the LPF cell is 2x times of the conventional cell.

This paper presents the study of drain induced barrier lowering (DIBL), threshold voltage roll-off ( V t roll-off) and current in Carbon nanotube Field-effect transistor (CNTFET). Analytical expressions for V t roll-off and electrostatic scale length λ have been derived under quantum capacitance limit. It is observed that electrostatic scale length is linearly proportional to (t ox /d) and CNTFET devices show less short channel effects (SCEs) than the Si-MOS devices. The derived current equation is different from the equation proposed in the literature. This equation is more efficient in predicting the current value for the ultra-deep submicron CNFET devices. The developed analytical expressions in this paper show an excellent matching with experimental and Monte-Carlo simulation results.

If you would like to write for this, or any other Emerald publication, then please use our Emerald for Authors service information about how to choose which publication to write for and submission guidelines are available for all. Please visit www.emeraldinsight.com/authors for more information. About Emerald www.emeraldinsight.comEmerald is a global publisher linking research and practice to the benefit of society. The company manages a portfolio of more than 290 journals and over 2,350 books and book series volumes, as well as providing an extensive range of online products and additional customer resources and services.Emerald is both COUNTER 4 and TRANSFER compliant. The organization is a partner of the Committee on Publication Ethics (COPE) and also works with Portico and the LOCKSS initiative for digital archive preservation. AbstractPurpose -Low power static-random access memories (SRAM) has become a critical component in modern VLSI systems. In cells, the bit-lines are the most power consuming components because of larger power dissipation in driving long bit-line with large capacitance. The cache write consumes considerable large power due to full voltage swing on the bit-line. The aim of the paper is to propose a new SRAM cell architecture to reduce the power consumption during write 0 and write 1 operation. Design/methodology/approach -The proposed circuit includes two tail transistors in the pull-down path of inv-A and inv-B. The simulated results of the proposed cell is compared with Conventional 6T SRAM cell and zero-asymmetric SRAM cell. Findings -The proposed SRAM cell consumes less power than the conventional SRAM cell during write operation. The write access delay is reported to be lower than conventional and ZA SRAMs in the proposed circuit. The read operation is similar to Conventional SRAM cell but due to tail transistors the read access delay and stability is poor in the present circuit which can be improved by careful transistors sizing. Originality/value -The paper proposes a SRAM cell to reduce the power in write "0" as well as write "1"operation by introducing two tail transistors.

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