In this paper, a complete study of the cell reliability based on a unique oxide damage characterization for two different programming schemes of p-channel flash cell will be presented. These two programming schemes are Channel Hot Electron (CHE) injection or Band-to-Band (BTB) tunneling induced hot electron injection. Degradation of memory cells after PIE cycles due to the above oxide damages has been identified. It was found that both Nit and Qox will dominate the device degradation during programming. Although p-flash cell has high speed performance by comparing with n-flash cell, extra efforts are needed for designing reliable p-channel flash cell by appropriate drain engineering or related device optimization.

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In this paper, we provide a methodology to evaluate the hot-carrier-induced reliability of flash memory cells after long-term program/erase cycles. First, the gated-diode measurement technique has been employed for determining the lateral distributions of interface state (N it) and oxide trap charges (Q ox) under both channel-hot-electron (CHE) programming bias and source-side erase-bias stress conditions. A gate current model was then developed by including both the effects of N it and Q ox. Degradation of flash memory cell after P/E cycles due to the above oxide damage was studied by monitoring the gate current. For the cells during programming, the oxide damage near the drain will result in a programming time delay, and we found that the interface state generation is the dominant mechanism. Furthermore, for the cells after long-term erase using source-side FN erase, the oxide trap charge will dominate the cell performance such as read-disturb. In order to reduce the read-disturb, source bias should be kept as low as possible since the larger the applied source erasing bias, the worse the device reliability becomes.

A new gate current model which considers the hotelectron induced oxide damage in n-MOSFET's was developed for the first time. The spatial distributions of oxide damage, including the interface state (N it ) and oxide trapped charge (Q ox ), were characterized by using an improved gated-diode current measurement technique. A numerical model feasible for accurately simulating gate current degradation due to the stress generated N it and Q ox has thus been proposed. Furthermore, the individual contributions of N it and Q ox to the degradation of gate current can thus be calculated separately using these oxide damage. For devices stressed under maximum gate current biases, it was found that the interface state will degrade the gate current more seriously than that of the oxide trapped charge. In other words, the interface states will dominate the gate current degradation under IG;max. Good agreement of the simulated gate current has been achieved by comparing with the measured data for pre-stressed and post-stressed devices. Finally, the proposed degradation model is not only useful for predicting the gate current after the hot-electron stress, but also provides a monitor that is superior to substrate current for submicron device reliability applications, in particular for EPROM and Flash EEPROM devices. Steve S. Chung (S'83-M'85-SM'95) received the B.S. degree and has been a Full Professor since Fall 1989. His current teaching and research interests are in the areas of device physics, deep-submicron CMOS VLSI technology, Spice device modeling, numerical simulation and modeling of submicron and deep-submicron MOS devices, SOI devices, nonvolatile memories and TFT's, characterization and reliability study of VLSI devices and circuits, and computational algorithms for VLSI circuits. He is a co-holder of several U.S. and R.O.C. patents.Dr. Chung has served on various technical program committees of IEEE ASIC Conference (U.S.), International Electron Devices and Materials Symposium (IEDMS, Taiwan), and HPC (High Performance Computing)-ASIA'95.

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