The evolution of the loading effect in Si1−xGex layers (0⩽x⩽20%) versus growth parameters has been investigated for selective and nonselective growth using silane- and dichlorosilane-based epitaxy. Various methods have been examined in order to reduce the loading effect, and their influence on the defect density will be further discussed. High-resolution x-ray diffraction and atomic force microscopy were applied as the main tools in these investigations. It is shown that SiGe epitaxy is strongly sensitive to the opening size on the patterned substrates. This dependence is affected by the chemistry of the deposition. This effect can be decreased by adding HCl to the gas mixture or decreasing the growth rate. Meanwhile, adding HCl during the growth of SiGe layers or using a low growth rate decreases the epitaxial quality of the layers. Depositing a Si seed layer prior to the growth of the SiGe layer reduces the loading effect without degrading the epitaxial quality of the layer.

The selective growth of Si-buffer/Si 1Ϫx Ge x /Si-cap structures (0.14 Ͻ x Ͻ 0.33) on patterned substrates aimed for channel layer applications in a metal-oxide-semiconductor field effect transistor structure was investigated. By optimizing the growth parameters the surface roughness of these structures was reduced. Furthermore, selective epitaxy of high B-or P-doped SiGe layers for source/drain applications was also studied. Abrupt dopant profiles with a good epitaxial quality and low sheet resistances, e.g., 195 and 260 ⍀/ᮀ for 420 Å thick, B-doped Si 0.81 Ge 0.19 and P-doped Si 0.71 Ge 0.29 layers, respectively, were obtained. In this study, secondary ion mass spectroscopy, high-resolution reciprocal lattice mapping, atomic force microscopy, and cross-sectional transmission electron microscopy were used as the main characterization tools.

PMOSFETs with a Si 0.7 Ge 0.3 channel were fabricated. The intrinsic gain of the Si 0.7 Ge 0.3 channel PMOSFET was compared to a reference Si PMOSFET, and was found to be enhanced by about 20 to 30 % for all gate lengths down to 0.3 m. This enhancement is attributed to an increased effective mobility in the Si 0.7 Ge 0.3 channel. The inclusion of a Si 0.7 Ge 0.3 channel was found to degrade neither the output conductance (g o ) nor the breakdown voltage.

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