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This RISC microprocessor is based on a microarchitecture designed in a 2.5V CMOS technology [l]. The 78.75mm2 design features dual 16kB instruction and data caches, a floating-point unit, an integer unit, a branch unit, a loadstore unit, and a system unit. Two instructions per cycle can be dispatched in this superscalar design. The user-configurable multiplying PLL provides a processor clock at 2X, 2.5X, 3X, 3.5X, 4X, 4.5X, 5X, 5.5X, and 6X the bus clock frequency. Testability features include level-sensitive-scan-design (LSSD), array-built-in-self-test (ABIST) logic for cache and tag arrays, and a JTAG interface [21. Figure 1 is a block diagram of the processor, and Figure 2, a micrograph.