Absttact ---Multiple tox is thoroughly investigated for nitrogen-implanted gate oxides with the optimization of QBD and a demonstration of 2-GHz counters. Furnace growth at 800°C, 85OoC, and 9OOOC is compared with rapid-thermal-oxidation (RTO) at 105OOC. A wide range of reduced growth rate, 20% to 80%, is achieved that meets the SIA road-map for the next few generations of the CMOS technology. Optimization of charge-to-breakdown (QBD) is achieved through investigation of the nitrogen distribution profile in the oxide that is affected by the growth temperature, nitrogen implant dose, and postoxidation anneals. 101%m2 nitrogen dose results in a higher QB as well as a tighter tail distribution of QBD than 5x10 /cm2 nitrogen dose. The tight distribution of QBD is important for yield improvement. If the oxide is either grown or annealed at 9OO0C, QBD is as good as the QBD of regular oxide without nitrogen. As an example of integration, 0.18-pm CMOS devices with dual gate oxides of 3 nm and 4 nm are fabricated and characterized at 1.5, 1.8, and 2.5 V. Performance of divide-by3 counters is evaluated with the consideration of parasitic RC delays, and the results are superior to the most recently published data. At room temperatures, the maximum toggle frequency (fT) is higher than 2 GHz for both 1.8 and 2.5 V operation, with a power dissipation of 3.4 pW at SOC. To further reduce the power dissipation to 0.08 pW, 1.5-V operation gives 1-GHz fT also at 85OC. A

We have demonstrated that the threshold voltage shifts in closely spaced, dual-poly CMOS devices are virtually eliminated by using buried, low energy gate implants. The reduced thermal budget lor gate activation, made possible by short dillusion distances, not only reduces dopant lateral diffusion in the gates but also in the device channel regions. Moreover, the process allows the use of thinner gate oxides and shallower junctions and improves the control of LM. IntroductionRecent advances in CMOS device isolation schemes make possible greatly increased device packing density. However, aggressive scaling of the PTOX-NTOX separation to submicron regime (0.4-0.6pn for 0.18pm CMOS) makes closely spaced P-and NMOS dual-poly devices with connected gates susceptible to cross-doping ellects, irrespective of the choice of the gate metal. Ai these dimensions, the device characteristics can be adversely affected by dopant lateral dillusion not only in the gate metal but also in the polysilicon layer itsell. In this work, we describe a novel processing scheme that ensures that dopant diffusion distances during gate drive-in and activation are much shorter than distanceshes needed lor dopant cross-diffusion, The gate structures are based on the concept of buried, ultra-low energy gate implants, utilizing the new generation of highcurrent, low energy ion implanters that have only recently become available 11).