Interface traps are shown to significantly affect the gateinduced drain leakage current in a MOSFET or gated diode. The leakage current in a p+ gated diode can increase by two orders of magnitude when the interface trap density is increased from 10" to l0l2 cm-'.eV-'. The fact that thermal annealing at 300°C can eliminate both the generated interface traps and the excessive leakage current supports the close correlation between the two. The p+ gated diode is found to be more snsceptible to this interface-trap-related leakage current than the n+ device, which can be explained qualitatively by an interface-trap-assisted tunneling model.

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We describe a new rapid thermal diffusion (RTD) process for shallow, heavily doped trench junctions in highdensity DRAM'S. Planar dopant soutees are formed by spincoating rigid substrates, such as silicon wafers or solid dopant sources, with liquid dopants. Di&lsion takes place at high temperatures when the source, placed in proximity to the silicon wafer, releases dopant via evaporation followed by diffusion to the silicon surface. Well-controlled, heavily doped shallow junctions are readily obtained for B, P, and As. The doping process is shown to provide uniform doping of high-aspect-ratio trenches.

During the last few years new DRAM products have been introduced at a rate of -4 yeardgeneration instead of 3. This trend will continue, Chip design efficiency (defined as the ratio between cell and total chip area) must be increased to >60-65% for 1Gb and beyond. Self-alignment schemes are essential for 64Mbit and beyond but after the first generation of 1Gb additional technology breakthroughs are needed for a cell area of less than 8F2 where F is design size. Conventional nitride storage dielectric, in conjunction with capacitor area enhancement techniques like HSG (hemispheric grain) and corrugated cylindrical poly electrodes, is applicable for 256Mbit and possibly first generation 1Gb. Barium strontium titanate will be used for 1Gb products and beyond.

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