A new electro-chemical mechanical polishing (ECMP) process was developed for SiC. This work focused on the n-type Si-face 4H-SiC (0001) substrates, with 8 ° off axis toward <1120>. Hydrogen peroxide (H 2 O 2 ) and potassium nitrate (KNO 3 ) solutions were used as the electrolytes while using colloidal silica slurry as the polishing medium for removal of the oxide. The current density during the polishing is varied from 10µA/cm 2 to over 20mA/cm 2 . At higher current flow (>20mA/cm 2 ), the final surface was rough whereas a smoother surface was obtained when the current density was in the vicinity of 1mA/cm 2 .

Double stacking faults (3C lamellae) formed by thermal processing of heavily (~3x10 19 cm -3 n-type) doped 4H-SiC substrates, with or without lightly n-doped epilayers, are characterized by low temperature photoluminescence (PL), Raman scattering, secondary electron imaging (SEI), and electrostatic force microscopy (EFM). Electric fields are evident in the SEI and EFM images where the faults intersect the surface. Self-consistent simulations including spontaneous polarization explain several features observed in PL and Raman spectra.

Selective growth of SiC on SiC substrate was demonstrated in a chemical vapor deposition (CVD) reactor using a new high temperature mask. Bulk 4H-SiC with 8 o miscut (0001) Si-face wafers were coated with the high temperature mask and patterned using standard photolithography. The pattern consisted of window stripes as spokes of a wheel. Epitaxial growth of SiC was carried out in a conventional, horizontal, rf-heated cold wall reactor at temperatures in the range 1450-1550 o C. When the window stripes are oriented along <1120> miscut direction, the growth on the exposed area followed the substrate orientation, and the top surface was smooth and specular. However, when the window stripes are aligned along <1100> direction (perpendicular to the miscut direction), the growth on the window stripes developed (0001) facets on the surface. Epitaxial lateral overgrowth over the mask was also studied by cross sectional scanning electron microscopy (SEM). It was found that the extent of lateral growth varied with the stripe orientation. Effects of growth temperature as well as silane flows on the selective growth were also studied. Higher temperature or lower silane flow results in the etching of exposed SiC instead of growth. The etched surfaces developed orientation dependent facets similar to the growth. Importantly, the mask could be easily removed after the growth.

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Using light emission imaging (LEI), we have determined that not all planar defects in 4H-SiC PiN diodes expand in response to bias. Accordingly, plan-view transmission electron microscopy (TEM) observations of these diodes indicate that these static planar defects are different in structure from the mobile stacking faults (SFs) that have been previously observed in 4H-SiC PiN diodes. Bright and dark field TEM observations reveal that such planar defects are bounded by partial dislocations, and that the SFs associated with these partials display both Frank and Shockley character. That is, the Burgers vector of such partial dislocations is 1/12<4-403>. For sessile Frank partial dislocations, glide is severely constrained by the need to inject either atoms or vacancies into the expanding faulted layer. Furthermore, these overlapping SFs are seen to be fundamentally different from other planar defects found in 4H-SiC.