A series of β-diketiminate Ni–NO complexes with a range of NO binding modes and oxidation states were studied by X-ray emission spectroscopy (XES). The results demonstrate that XES can directly probe and distinguish end-on vs side-on NO coordination modes as well as one-electron NO reduction. Density functional theory (DFT) calculations show that the transition from the NO 2s2s σ* orbital has higher intensity for end-on NO coordination than for side-on NO coordination, whereas the 2s2s σ orbital has lower intensity. XES calculations in which the Ni–N–O bond angle was fixed over the range from 80° to 176° suggest that differences in NO coordination angles of ∼10° could be experimentally distinguished. Calculations of Cu nitrite reductase (NiR) demonstrate the utility of XES for characterizing NO intermediates in metalloenzymes. This work shows the capability of XES to distinguish NO coordination modes and oxidation states at Ni and highlights applications in quantifying small molecule activation in enzymes.

In order to understand the effect of the interface on the spin pumping and magnetic proximity effects, high resolution transmission electron microscopy and ferromagnetic resonance (FMR) were used to analyze Py/Pt bilayer and Pt/Py/Pt trilayer systems. The samples were deposited by dc magnetron sputtering at room temperature on Si (001) substrates. The Py layer thickness was fixed at 12 nm in all the samples and the Pt thickness was varied in a range of 0-23 nm. A diffusion zone of approximately 8 nm was found in the Py/Pt interfaces and confirmed by energy dispersive X-ray microanalysis. The FMR measurements show an increase in the linewidth and a shift in the ferromagnetic resonance field, which reach saturation. V C 2015 AIP Publishing LLC.

Field Programmable Gate Arrays (FPGA) are integrated circuits (ICs) which can implement virtually any digital function and can be configured by a designer after manufacturing. This is beneficial when dedicated application-specific runs are not time or cost-effective; however, this flexibility comes at the cost of a substantially higher interconnect overhead. Three-dimensional (3D) integration can offer significant improvements in the FPGA architecture by stacking multiple device layers and interconnecting them in the third or vertical dimension, through a substrate, where path lengths are greatly reduced. This will allow for a higher density of devices and improvements in power consumption, signal integrity, and delay. Further, it facilities heterogeneous integration where additional functionalities can be incorporated into the same package as the FPGA, such as sensors, memories, and RF/analog or photonic chips, etc. Traditionally, devices have always been laid out in a planar format. 3D integration is an architecture wherein multiple layers of planar devices are stacked and interconnected using through silicon vias (TSVs) in the vertical direction. This work will specifically detail the development of a processing and fabrication route for a three-dimensional asynchronous field programmable gate array (3D-AFPGA) design based on an extension of preexisting 2D-FPGA tile designs. Since thermal management of 3D-AFPGA is important, numerical simulations performed to predict the temperature distribution and avoid the maximum junction temperature. The numerical thermal modeling for predicting the equivalent thermal conductivity in every layer and three-dimensional temperature fields in the 3D-AFPGA are developed and discussed.

This work will specifically detail the development of a processing and fabrication route for a three-dimensional asynchronous field-programmable gate array (3D-AFPGA) design based on an extension of pre-existing two-dimensional-field-programmable gate array (2D-FPGA) tile designs. The periodic nature of FPGAs permits the use of an alternative approach, whereby the design entails splitting the FPGA design along tile borders and inserting through silicon vias (TSVs) at regular spatial intervals. This serves to enable true 3D performance (i.e., full 3D signal routing) while leaving most of the 2D circuit layouts intact. 3D signal buffers are inserted to handle communication between vertical and adjacent neighbors. For this approach, the density of vertical interconnections was shown to be determined by the size of the bond pads used for tier–tier communications and bonding. As a consequence, reducing bond pad dimensions from 25 μm to 15 μm, or 10 μm, bond pads are preferred to increase the connectivity between layers. A 3D-AFPGA mockup test structure was then proposed for completing development and exercising the 3D integration process flows. This mockup test structure consists of a three-tier demonstration vehicle consisting of a chip-to-wafer and a subsequent chip-to-chip bond. Besides, an alternate copper bonding approach using pillars was explored. Although the intended application is for the 3D integration process compatible with the 3D AFPGA design, the test structure was also designed to be generally applicable to various applications for 3D integration. Because of the importance of thermal management of 3D-AFPGA, it is important to predict the temperature distribution and avoid the maximum junction temperature. The numerical thermal modeling for predicting the equivalent thermal conductivity in every layer and the 3D temperature distribution in the 3D-AFPGA are developed and discussed as well.

Recent work has shown that graphene, a 2D electronic material amenable to the planar semiconductor fabrication processing, possesses tunable electronic material properties potentially far superior to metals and other standard semiconductors. Despite its phenomenal electronic properties, focused research is still required to develop techniques for depositing and synthesizing graphene over large areas, thereby enabling the reproducible mass-fabrication of graphene-based devices. To address these issues, we combined an array of growth approaches and characterization resources to investigate several innovative and synergistic approaches for the synthesis of high quality graphene films on technologically relevant substrate (SiC and metals). Our work focused on developing the fundamental scientific understanding necessary to generate large-area graphene films that exhibit highly uniform electronic properties and record carrier mobility, as well as developing techniques to transfer graphene onto other substrates.4