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As the supply voltage is reducing with feature size, SRAM cell design is going through severe stability issues. The issue becomes worse due to increased variability in below sub-100 nm technology. In this paper, we present a highly stable 2-port 8T SRAM cell for high speed application in 65 nm technology. The proposed design provides high stability under simultaneous read/write disturbed access without reducing the I cell . The cell characteristic is extensively examined under random variation. The dynamic read noise margin is improved by 95% over conventional dual port SRAM. The zero-precharge sensing and virtual ground scheme reduce read path leakage current by 95% over conventional high precharge 2-port SRAM cell. The cell current is improved by 52% over conventional design. Finally, an 8 Kb bit-interleaved 2-stage pipelined SRAM architecture is presented using proposed cell. The 2-stage pipeline architecture provides data transfer bandwidth of 3.1 GB/s. Area-efficient 2-stage decoder layout helps to avoid pseudo read problem in unselected cells without sacrificing memory access time.