Abstract-WLP (Wafer level packaging) for image sensor device has the advantage of small size, high performance and low cost. In WLP technology, in order to establish electrical interconnection from image sensor contact pad to the backside of the wafer, several structures have been developed, such as T-contact and TSV (Through Silicon Via). In this paper, a wafer level package of image sensor with new type TSV electrical interconnection for image sensor pad is presented. The target of this development is to reduce process cost and difficulty, and to increase yield of image sensor packaging. Key fabrication processes include glass protecting wafer bonding, device wafer thinning, backside through via etching, via passivation layer deposition, pad oxide opening, via filling and backside re-routing layer formation, etc. Compared to large opening area of tapered via on the backside of CMOS image sensor wafer, only small opening area is needed for making via interconnection with vertical sidewall presented in this paper. A fillet structure at bottom corner of via holes can help to reduce sequent process difficulty, so that low-cost and simplified unit processes are successfully adopted in the fabrication process for through via formation. The through via interconnection shows good electrical connection performance, and high-quality photo images are obtained by packaged image sensor device.

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WLP (Wafer level packaging) for image sensor device bas tbe advantage of small size, higb performance and low cost. In WLP tecbnology, in order to estabUsb electrical interconnection from image sensor contact pad to tbe backside of tbe wafer, several structures bave been developed, sucb as T-contact and TSV (Tbrougb SiUcon Via). In tbis paper, a wafer level package of image sensor witb new type TSV electrical interconnection for image sensor pad is presented. Tbe target of this development is to reduce process cost and difficulty, and to increase yield of image sensor packaging. Key fabrication processes include glass protecting wafer bonding, device wafer thinning, backside tbrougb via etching, via passivation layer deposition, pad oxide opening, via filling and backside re-routing layer formation, etc. Compared to large opening area of tapered via on tbe backside of CMOS image sensor wafer, only small opening area is needed for making via interconnection witb vertical sidewall presented in this paper. A fdlet structure at bottom corner of via boles can belp to reduce sequent process difficulty, so tbat iow-cost and simplified unit processes are successfully adopted in tbe fabrication process for tbrougb via formation. Tbe tbrougb via interconnection sbows good electrical connection performance, and higb-quaUty pboto images are obtained by packaged image sensor device.I.

Using thermal wave mapping and imaging techniques in conjunction with x-ray transmission topography and transmission electron microscopy, precipitation behavior of various fast and slowly diffusing metallic impurities such as Au, Co, Cu, Fe, Mo, Ni, Pd, Pt, W and Zn in Czochralski Si following rapid thermal processing are investigated. Our data have shown that thermal wave signal is sensitive to certain types of metal-induced surface defects (most likely metal silicides) and associated crystallographic defects. In addition, the comparison between thermal wave and x-ray imaging methods shows an interesting speciesdependent complimentary relationship.