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Overlay continues to be one of the key challenges for photolithography in semiconductor manufacturing. It becomes even more challenging due to the continued shrinking of the device node. The corresponding tighter overlay specs require the consideration of new paradigms for overlay control, such as high-order control schemes and/or field-by-field overlay control. These approaches have been demonstrated to provide tighter overlay control for design rule structures, and can be applied to areas such as double patterning lithography (DPL), as well as for correcting non-linear overlay deformation signatures caused by non-lithographic wafer processing. Previously we presented a study of high-order control applied to high order scanner correction, high order scanner alignment, and the sampling required to support these techniques. Here we extend this work, using sources of variation (SOV) techniques, and have further studied the impact of field by field compensation. This report will show an optimized procedure for high order control using production wafers and field by field control.

To extend the limitation of KrF lithography into the 110 nm design rule region, dipole off-axis illumination (OAI) is suggested. We have investigated the availability of the 1st-order efficiency as a method of optimization and confirmed it in the conventional OAI. By the 1st-order-efficiency method, we have designed two dipole apertures that are capable of resolving horizontal and vertical dense patterns, and have evaluated the basic performance of the modified dipole apertures. To verify the applicability of the modified dipole apertures to memory devices, we tested a variety of patterns and obtained fine patterns with the help of optical proximity correction (OPC). In this study, we found that the optimized dipole OAI can serve as an extension method of KrF lithography for 110 nm devices.

Overlay continues to be one of the key challenges for lithography in advanced semiconductor manufacturing. It becomes even more challenging due to the continued shrinking of the device node. Some low k1 techniques, such as Double Exposure and Double Patterning also add additional loss of the overlay margin due to the fact that the single layer pattern is created based on more than 1 exposure. Therefore, the overlay between 2 exposures requires very tight overlay specification.Mask registration is one of the major contributors to wafer overlay, especially field related overlay. We investigated mask registration and wafer overlay by co-analyzing the mask data and the wafer overlay data. To achieve the accurate cohesive results, we introduced the combined metrology mark which can be used for both mask registration measurement as well as for wafer overlay measurement. Coincidence of both metrology marks make it possible to subtract mask signature from wafer overlay without compromising the accuracy due to the physical distance between measurement marks, if we use 2 different marks for both metrologies. Therefore, it is possible to extract pure scanner related signatures, and to analyze the scanner related signatures in details to in order to enable root cause analysis and ultimately drive higher wafer yield. We determined the exact mask registration error in order to decompose wafer overlay into mask, scanner, process and metrology. We also studied the impact of pellicle mounting by comparison of mask registration measurement pre-pellicle mounting and post-pellicle mounting in this investigation.

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