Thrombocytopenia developed in some individuals treated with a recombinant thrombopoietin (TPO), pegylated recombinant human megakaryocyte growth and development factor (PEG-rHuMGDF). Three of the subjects who developed severe thrombocytopenia were analyzed in detail to determine the cause of their thrombocytopenia. Except for easy bruising and heavy menses, none of these subjects had major bleeding episodes; none responded to intravenous immunoglobulin or prednisone. Bone marrow examination revealed a marked reduction in megakaryocytes. All 3 thrombocytopenic subjects had antibody to PEG-rHuMGDF that cross-reacted with endogenous TPO and neutralized its biological activity. All anti-TPO antibodies were immunoglobulin G (IgG), with increased amounts of IgG4; no IgM antibodies to TPO were detected at any time. A quantitative assay for IgG antibody to TPO was developed and showed that the antibody concentration varied inversely with the platelet count. Anti-TPO antibody recognized epitopes located in the first 163 amino acids of TPO and prevented TPO from binding to its receptor. In 2 subjects, endogenous TPO levels were elevated, but the TPO circulated as a biologically inactive immune complex with anti-TPO IgG; the endogenous TPO in these complexes had an apparent molecular weight of 95 000, slightly larger than the fulllength recombinant TPO. None of the subjects had atypical HLA or platelet antigens, and the TPO cDNA was normal in both that were sequenced. Treatment of one subject with cyclosporine eliminated the antibody and normalized the platelet count. These data demonstrate a new mechanism for thrombocytopenia in which antibody develops to TPO; because endogenous TPO is produced constitutively, thrombocytopenia ensues. (Blood. 2001;98:3241-3248)

Analog hardware architecture of a memristor bridge synapse-based multilayer neural network and its learning scheme is proposed. The use of memristor bridge synapse in the proposed architecture solves one of the major problems, regarding nonvolatile weight storage in analog neural network implementations. To compensate for the spatial nonuniformity and nonideal response of the memristor bridge synapse, a modified chip-in-the-loop learning scheme suitable for the proposed neural network architecture is also proposed. In the proposed method, the initial learning is conducted in software, and the behavior of the software-trained network is learned by the hardware network by learning each of the single-layered neurons of the network independently. The forward calculation of the single-layered neuron learning is implemented on circuit hardware, and followed by a weight updating phase assisted by a host computer. Unlike conventional chip-in-the-loop learning, the need for the readout of synaptic weights for calculating weight updates in each epoch is eliminated by virtue of the memristor bridge synapse and the proposed learning scheme. The hardware architecture along with the successful implementation of proposed learning on a three-bit parity network, and on a car detection network is also presented.

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