2.5D integration is achieved using inductive coupling in place of bump connections. The size of the interposer is less than 1/34 that of conventional technology, leading to cost saving without compromising area and energy efficiency. A 40 nm CMOS test chip is fabricated and data-transfer performance of 317 Gb/s/mm2, 1.2 pJ/b is measured. Moreover, it is shown the area and energy efficiency of this technique could be improved more than linearly in accordance with the technology scaling rules.

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