A wirelength-driven placer without considering routability could introduce irresolvable routing-congested placements. Therefore, it is desirable to develop an effective routability-driven placer for modern mixed-size designs employing hierarchical methodologies for faster turnaround time. This paper presents a novel two-stage technique to effectively identify design hierarchies and guide placement for better wirelength and routability. To optimize wirelength and routability simultaneously during placement, a new analytical net-congestion-optimization technique is also proposed. Compared with the participating teams for the 2012 ICCAD Design Hierarchy Aware Routability-driven Placement Contest, our placer can achieve the best quality (both the average overflow and wirelength) and the best overall score (by additionally considering running time).

We present a new floorplan representation, called circular-packing trees (CP-trees), for the problem of macro placement. Our CPtrees can flexibly pack movable macros toward corners or preplaced macros along chip boundaries circularly to optimize macro positions/orientations for better wirelength and routing congestion. Unlike previous macro placers that often consider only the interconnections among macros, we develop a routability-aware wirelength model to fast estimate the wirelength among macros and standard cells and to consider macro porosity effects for better routability. Compared with leading academic mixed-size placers, experimental results show that our algorithm can achieve the shortest routed wirelength for industrial benchmarks.

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