Graphics image files can be stored in different file formats. One of the most general form is bitmap image format. Bitmap file format is an uncompressed form of image consisting of matrix of pixel constructing the image. BMP (24bit) represents each pixel in set of 24 bits comprising of RGB(Red, Green, Blue). Where BMP(32bit) represents one additional byte of alpha for transparency/opaque. Researcher identified redundancy of colors and made model to compress BMP(24bit) file. A model is developed to list all unique color of the image and store only index of these unique color instead of the whole 3 RGB color. The compression performance is based on number of unique colors and width-height of the image. In this paper researcher has made an effort to extract such bit patterns representing the pixel and then using such different bit patterns determines the total number of colors represented in image. Once the number of color is found it is possible to compress the file by grouping similar colors with exact pixel positions. Paper is prepared based on the research to analyze the image file and then compressing it. The model demonstrated here for 24bit file and at last concluded with tradeoff, improvements and limitation.

Abstract-The progress of programmable logic devices such as FPGA makes it realize the digital control system without microprocessor recently. A very complex control algorithm can be implemented into FPGA and the calculation time can be dramatically reduced based on parallel processing hardware circuit. In this paper, a design conceptual of original FPGA-based controller for high speed train system is proposed. The Cyclone-II EP2C35F672C6 with EPCS16 16-Mbit serial configuration device is based on SRAM technology and nine embedded array blocks (EABs) are implemented. Based on the simulation result and hardware implementation, the FPGA speed controller has very good performance in controlling high speed train system. Index Terms-Controller, field programmable gate array (FPGA), hardware, high speed train. I. INTRODUCTIONAll high-speed railway systems have brought up many new and challenging technical issues as well as commercial issues such as transport capacity, comfort and safety. The railway systems can work with high security and high efficiency are mainly depended on the core of the train control systems. Much effort has been made to study, understand and analyze on automatic train control systems over the years [1]-[3]. It is a typical complex dynamic system with large time delays, a high nonlinearity and multi objectives, which is under time-varying and uncertain conditions on such parameters as traction power supplies, different type of signals, speed restrictions, braking and so on. In real operation, different situations imply different control demands for different purposes, while the main objectives are always on-time scheduling, high speed motion, full load and most important safe operation of the train. A high-speed train motion and operation is a complicated, complex system and process, involving locomotive dynamics, communications and signaling, rail track, etc. for which simulation systems provide a practical platform for design, testing and analysis [4], [5]. Due to the high complexity and diversity of automatic train control systems, good computer based simulation tools for evaluation of the effectiveness of new protocols and the feasibility of new applications are greatly Manuscript received September 15, 2012; revised October 12, 2012 importance.An FPGA is a device that contains a matrix of reconfigurable gate array logic circuitry. When an FPGA is configured, the internal circuitry is connected in a way that creates a hardware implementation of the software application. FPGA technology provides the reliability of dedicated hardware circuitry, true parallel execution, and lightning-fast closed-loop control performance. As a result, the performance of one part of the application is not affected when additional processing is added. Also, multiple control loops can run on a single FPGA device at different rates. FPGA-based control systems can enforce critical interlock logic and can be designed to prevent I/O forcing by an operator. However, unlike hard-wired printed circuit board (PCB) design, w...

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