Pre-bond testing of silicon interposer is difficult due to the large number of nets to be tested and small number of test access ports. Recently, it was proposed to include a test interposer that is contacted with the interposer under test in the testing process. Combining these two interposers provides access to nets that are not normally accessible. Previous synthesis method for test interposer was based on constrained breadth-first search, which can be time-consuming. Besides, separate test interposers have to be provided for open and short fault testing. In this paper, we present a theoretical study on the topology of testable circuit structure for interconnect faults in silicon interposer. Based on the theoretical framework, a more efficient synthesis method is developed. Furthermore, a single test interposer can be used for both open and short fault detection, which leads to shorter test time and lower test cost.

This paper presents a novel scheme for silicon interposer testing. Testing interpose is difficult due to the large number of nets to be tested and small number of test access ports. Thus, previous method can only achieve limited fault coverage for open faults. We propose to include a test interposer that will be contacted with the interposer under test in the testing process. Combining these two interposers will provide access to nets that are not normally accessible; thus, most or all nets become testable. Furthermore, both open and short faults in the interconnect structure can be tested. The efficiency of the proposed test scheme is mainly affected by the structure of test interposer; thus, algorithms for the generation of optimized test interposers are explored. Experimental results show that all faults can be efficiently tested with the proposed method.

No abstract

No abstract