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Many redundancy based hardened latch would become invalid when multiple nodes collect charge concurrently. To mitigate multi-node charge collection, a novel latch based on the combinational of layout and circuit design is proposed. The number of sensitive node pairs is reduced by the circuit design. And by adjusting the placement the sensitive transistors in the layout, the distance between sensitive transistors is increased. SPICE simulation results illustrate that the proposed latch significantly reduce the number of sensitive node pairs. The performance of mitigating multinode charge collection is improved.

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