This paper describes a new formulation to generate robust tests for path delay faults in combinational circuits based o n B o olean satisability. Conditions to detect a target path delay fault are r epresented b y a Boolean formula. Unlike the technique described in [16], which extracts the formula for each path delay fault, the proposed formulation needs to extract the formula only once for each circuit cone. Experimental results show tremendous time saving on formula extraction compared to other satisability-based A TPG algorithms. This also leads to low test generation time, especially for circuits that have many paths but few outputs. The proposed formulation has also been modied to generate other types of tests for path delay faults.

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