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In this paper we present a generic Network Security Processor (NSP) design suitable for a wide range of security related protocols in wired or wireless network applications. Following the platform-based design methodology, we develop four specific platforms, i.e., architecture platform, EDA platform, Design-for-Testability (DFT) platform, and prototyping platform, for our NSP design. With these platforms, design of the NSP chip becomes more efficient and systematic. A prototype chip of the NSP has been implemented and fabricated with a 0.18µm CMOS technology. The chip area is 5mm×5mm (with 1M gates approximately), including I/O pads. The operating clock rate is 80MHz. The best performance of the crypto-engines is 1.025Gbps for AES, 1.652Mbps for RSA, 125.9/157.65Mbps for HMAC-SHA1/MD5, and 2.56Gbps for random number generator. Comparison result shows that our NSP is efficient in terms of performance, flexibility and scalability.

This paper presents a security processor to accelerate cryptographic processing in modern security applications. Our security processor is capable of popular cryptographic functions such as RSA, AES, hashing and random number generation, etc. With proposed Crypto-DMA controller, data gathering and scattering become flexible for security processing, using a simple descriptor-based programming model. The architecture of the security processor with its core-based platform is scalable and configurable for security variations in performance, cost and power consumption. Different number of data channels and cryptoengines can be used to meet the specifications. In addition, a DFT platform is also implemented for the design-test integration. The security processor has been fabricated with 0.18 m CMOS technology. The core area is ¿ ÑÑ ¢ ¾ ¾ ÑÑ (525K gates approximately) and the operating clock rate is 83MHz.