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In this paper, we propose a novel, efficient VLSI architecture for the implementation of one-dimension, lifting-based discrete wavelet transform (DWT). Both of the folded and the pipelined schemes are applied in the proposed architecture; the former scheme supports higher hardware utilization and the latter scheme speed up the clock rate of the DWT. The architecture has been coded in Verilog HDL, then verified successfully by the platform of Quartus-II of version 5.0. Finally, it was realized with the FPGA device of Cyclone family from Altera Corp.

In this paper, we propose an efficient VLSI architecture for implementing the forward two-dimensional discrete wavelet transform (2D DWT), which is computed without utilizing the traditional method of rows-by-columns or columns-by-rows. On account of the relation form within the original data, we apply masks of different window sizes to the transform and design the architecture based on these different window masks. On the comparison of the computing time, the proposed architecture requires only N*N/4 clock cycles for an N*N image, while it takes N*N clock cycles for the traditional row-by-column/column-by-row 2D DWT. The proposed architecture has a better performance than other designs reported in the literature.