The numerically controlled oscillator (NCO) is one of the digital oscillator signal generators. It can generate the clocked, synchronous, discrete waveform, and generally sinusoidal. Often NCOs care utilized in the combinations of digital to analog converter (DAC) at the outputs for creating direct digital synthesizer (DDS). The network on chips (NOCs) are utilized in various communication systems that are fully digital or mixed signals such as synthesis of arbitrary wave, precise control for sonar systems or phased array radar, digital down/up converters, all the digital phase locked loops (PLLs) for cellular and personal communication system (PCS) base stations and drivers for acoustic or optical transmissions and multilevel phase shift keying/frequency shift keying (PSK/FSK) modulators or demodulators (modem). The basic architecture of NCO will be enhanced and improved with less hardware for facilitating complete system level support to various sorts of modulation with minimum FPGA resources. In this paper design and memory optimization of hybrid gate diffusion input (GDI) numerically controlled oscillator based on field programmable gate array (FPGA) is implemented. compared with NCO based 8-bit microchip, memory optimization of hybrid GDI numerically controlled oscillator based on FPGA gives effective outcome in terms of delay, metal-oxide-semiconductor field-effect transistors (MOSFET’s) and nodes.

In this paper, the design and analysis of dual-mode numerically controlled oscillators (NCO) based controlled oscillator frequency Modulation is implemented. Initially, input is given to the analog to digital (ADC) converter. This will change the input from analog to digital converter. After that, the pulse skipping mode (PSM) logic and proportional integral (PI) are applied to the converted data. After applying PSM logic, data is directly transferred to the connection block. The proportional and integral block will transfer the data will be decoded using the decoder. After decoding the values, it is saved using a modulo accumulator. After that, it is converted from one hot residue (OHR) to binary converter. The converted data is saved in the register. Now both data will pass through the gate driver circuit and output will be obtained finally. From simulation results, it can observe that the usage of metal oxide semiconductor field effect transistors (MOSFETs) and total nodes are very less in dual-mode NCO-based controlled oscillator frequency modulation.

<span lang="EN-US">Gate diffusion input (GDI) is a technique, which enables reducing power consumption, area and delay in the digital circuits significantly, at the same time maintains low complexity of the logical design. This paper focuses on the analysis and interpretation of the design and implementation of GDI-based pipeline architecture for numerically controlled oscillator (NCO) using look up table (LUT). Based on the input signal and the alternate signal, this phase separation will separate the phase difference signal. The NCO generates a frequency and phase harmonized output signal with an antecedence fixed frequency clock. The 32-bit counter then compares the current count to the value stored in the compare register. Here the Coherent control comes into picture. It controls the carrier synchronizer by employing data from the 32-bit counter and the obtained data will be saved. It is updated and advanced using the third peer group of frequency synthesis technology. The test outcomes are accompanied with the theoretical concept and reproduced the results. The main objective of GDI-based pipeline architecture for NCO using LUT is to reduce the usage of metal oxide semiconductor field effect transistors (MOSFET’s). NCO is an indispensable component in many digital communication systems linked to modems, software-defined radios, and digital radio, digital down/upconverters for cellular and personal communications service base stations.</span>

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