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This work aims at answering to the 3D mega trend of silicon based platform and 3D wafer level packaging (3D-WLSiP). We focus on the development of architectures compliant with high volume markets for applications like mobile telecommunication. In this market, the silicon material will remain the key platform for 3D integration and has to offer the vertical interconnection as well as ultra-thin packages to fit into very slim electronic devices. We have designed both a mechanical demonstrator with daisy chains and a fully functional product based on a silicon interposer, focusing on forward and backward compatibility between Front-End and 3D packaging and the development of a complete set of advanced technological modules: -Thru-silicon-via interconnections (TSV) with copper viamid technologies.-Ultra-thin (20 and 35 µm) chips fabrication using dicing before grinding (DBG) with 45° beveled edge and plasma stress release technology.-Thin chips stack on the TSV interposer before processing the back side (stacking first) with two different approaches. The first one is a flip chip integration based on Cu/SAC µbumps while the second is the Back-to-Face (B2F) way based on high topology RDL after permanent bonding of the chips face up on the interposer. Chip bonding is done with several materials either on die side with die attach film (DAF) or on interposer side using wafer level spin coated polymers. -Thin wafer handling using advanced temporary bonding process to handle the thin silicon interposer wafers during the integration based on BSI product from Brewer Science and ZoneBOND™ technology. Moreover different strategies of handling have been investigated involving high topology temporary bonding as well as carrier flip-flop approaches.-Thin wafer level packaging (TWLP) has been implemented sequentially on front side and back side of the thin resulting in a fully 3D-WLSiP module.Thermo-mechanical FEM simulation and first reliability assessment using mechanical demonstrator have been carried out and support the good mechanical behaviour of the integration.Electrical tests have been also completed that allows comparing the performances of F2F and B2F interconnection schemes in terms of resistances and yield at front side level but also at back side level after TSV exposure, RDL and bumps. Successful results of development loops have led to start processing a full functional product benefiting of the best process flow.

Chip-to-wafer stacking is a key enabling technology for 2.5D as well as for 3D with technological challenges driven by on one hand the increase of the die surface and the number of I/Os and on the other hand by the reduction of the vertical dimensions. In our integration, the chips are reported on a silicon interposer containing copper via-middle TSVs. Two different approaches have been considered to realize chip-to-wafer stacking with respectively 35 and 20 μm ultra-thin dies. The first one is the conventional flip chip (or Face-to-Face, F2F) integration based on Cu/SAC μ-pillar connections while the second is a less classical Back-to-Face (B2F) way based on the realization of a high topology RDL after bonding the chips face up on the silicon interposer using a polymer. This last architecture becomes more and more attractive with the reduction of the chip thickness to ultra-thin dimension and can offer substantial advantages in terms of design flexibility and technology cost. Chip bonding is one of the first tasks to address: several bonding materials have been tested either on die side using die attach film (DAF) or on bottom interposer side using wafer level spin coated polymers. Then a novel brick consisting of high topology encapsulation and metallization has been fully developed to connect the dies to the bottom wafer enabled by the development of a specific lithography process. Thermo-mechanical FEM simulation and first reliability assessment have been carried out and support the good mechanical behavior of this integration. Electrical tests have been also completed that allows comparing the performances of F2F and B2F interconnections in terms of resistances and yield at front side level but also at back side level after TSV exposure. Back to Face integration can be very attractive in terms of process complexity and cost for ultra-thin chips with limited I/Os counts.

3D Integrated Passive and Actives Component (IPAC) is a new concept of ultra-miniaturized and highly functional sub-systems, which enables one to achieve higher RF functionality in a single module. As the first step, this paper demonstrates the concept of integrating passive components using 100μm ultra-thin glass and small Through Package Vias (TPVs) by ArF excimer laser. Passive low pass filters (LPF) for WLAN in thin dielectrics on glass were designed using circuit simulator and EM solver. The LPFs were fabricated using low-cost panel based processes, and then assembled onto the Printed Wiring Board (PWB). The filters on either side of the glass interposer were measured at the board level, and the results corroborated well with EM simulations. The measurement results showed low insertion loss (about −1dB) and high rejection (<−20dB). The integration of passive components using double-side and ultra-thin glass interposers with small TPVs, enables one to shrink RF module size.