No abstract

No abstract

No abstract

A GeNi alloy diffusion barrier for contacts on bismuth antimony telluride is proposed. Multiple gold contact diffusion barriers were tested at different thermal aging conditions in air and reducing atmospheres. Among all diffusion barriers, the GeNi alloy barrier shows the best performance for bulk samples with no substantial degradation of the contact resistance, no contact color change, and no change of thermoelectric properties. We observed D Au–GeNi = (9.8 ± 2.7) × 10 –20 m 2 /s within the GeNi alloy barrier, which is 4 times smaller than D Au–BiSbTe . The presence of the initial Ge layer also proves to be effective in reducing nickel diffusion yielding D Ni–BiSbTe = (8.57 ± 0.49) × 10 –19 m 2 /s. During GeNi alloy formation, Ge diffusion into BiSbTe produces GeTe, which apparently blocks the van der Waals gaps eliminating Au and Ni fast diffusion pathways. Thermal aging of BiSbTe nanowires shows that Au and Ni diffusion degrades the thermoelectric power factor, whereas the GeNi alloy barrier sample is mostly preserved. The GeNi alloy barrier is a reliable solution to long-term thermal applications of BiTe-based materials.

Cracking of multilayer ceramic chips due to mechanical and thermal stresses during surface mounting is a major problem. Two types of tests were performed to study the susceptibility of chips for thermal shock cracking. In one test, chips were immersed in molten solder at different temperatures and, after cooling, chips were examined for visible cracks. In another test, chips were mounted on a printed circuit board and, then, wave soldered to simulate the actual usage conditions. After the soldering process, chips were exposed to load humidity conditions and, then, tested for insulation resistance. Cracked chips from both tests were analyzed by fractographic methods to determine the source of failure. Causes of the defects leading to fracture and their relationship to the processing of multilayer capacitors are discussed. The relative advantages and disadvantages of the two thermal shock test methods in evaluating the integrity of the chips are presented. [