In this paper, an analytical model of a proposed low-cost high efficiency NPN silicon-based solar cell structure is presented. The structure is based on using low cost heavily doped commercially available silicon wafers and proposed to be fabricated by the same steps as the conventional solar cells except an extra deep trench etch step. Moreover, the cell has been engineered to react to the UV spectrum, resulting in a greater conversion performance. The presented analytical model takes the electrical and optical characteristics into account. Thus, the influence of both physical and technological parameters on the structure performance could be easily examined. Consequently, the optimization of the structure performance becomes visible. To inspect the validity of the analytical model, a comparison of the main performance parameters resulting from the model results with TCAD simulations is carried out showing good agreement.

Perovskite solar cells (PSCs) have drawn significant consideration as a competing solar cell technology because of the drastic advance in their power conversion efficiency (PCE) over the last two decades. The interfaces between the electron transport layer (ETL) and the absorber layer and between the absorber layer and the hole transport layer (HTL) have a major impact on the performance of the PSCs. In this paper, we have investigated the defect interfaces between ETL/absorber layer and absorber layer/HTL of calibrated experimental lead-based and lead-free PSCs. The influence of the defect interfaces is studied in order to find the optimum value for the maximum possible PCE. While the PCE has not been enhanced considerably for the lead-based, it is boosted from 1.76% to 5.35% for lead-free PSCs. Also, bulk traps were found to have minor role in comparison with interface traps for the lead-free cell while they have a significant impact for the lead-based cell. The results presented in this work would shed some light on designing interface defects of various types of practical PSC structures and demonstrates the crucial impact of the interface defects on lead-free vs lead-based PSCs. All simulation studies are performed by using SCAPS-1D simulator.

In this paper, we study the effects of short channel on double gate MOSFETs. We evaluate the variation of the threshold voltage, the subthreshold slope, the leakage current and the drain-induced barrier lowering when channel length LCH decreases. Furthermore, quantum effects on the performance of DG-MOSFETs are addressed and discussed. We also study the influence of metal gate work function on the performance of nanoscale MOSFETs. We use a self-consistent Poisson-Schrödinger solver in two dimensions over the entire device. A good agreement with numerical simulation results is obtained.

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