We experimentally demonstrate DC functionality of graphene-based hot electron transistors, which we call graphene base transistors (GBT). The fabrication scheme is potentially compatible with silicon technology and can be carried out at the wafer scale with standard silicon technology. The state of the GBTs can be switched by a potential applied to the transistor base, which is made of graphene. Transfer characteristics of the GBTs show ON/OFF current ratios exceeding 10(4).

Nanoscale platinum films are deposited by atomic layer deposition using trimethylmethylcyclopentadienyl-platinum and oxygen as precursors on the high-k dielectrics ZrO 2 and Al 2 O 3 , respectively, and on SiO 2 , issuing deposition temperature and precursor ratios. The ALD-grown platinum films are polycrystalline and show a preferential (1 1 1) orientation. The films are homogeneous with a root mean square roughness of 0.6-0.7 nm and reveal a low resistivity of 13.2 μ cm. The effective work functions are 4.76 eV for ZrO 2 , 5.22 eV for Al 2 O 3 and 5.52 eV for SiO 2 . It is remarkable that the deposition temperature of the platinum metal gate influences the final equivalent oxide thickness. Comparing both, PVD and ALD platinum films, a decreased leakage current density is observed for the ALD films depending on ALD process conditions, along with an increase in the equivalent oxide thickness.

We investigate ultrathin ZrO2/La2O3 high-k dielectric stacks on germanium grown by atomic layer deposition. La2O3 is deposited from tris(N,N′-diisopropylformamidinate)-lanthanum and oxygen. Interfacial layer-free oxide stacks with a relative dielectric constant of 21 and equivalent oxide thickness values as low as 0.5 nm are obtained. Metal oxide semiconductor capacitors with platinum as the gate electrode exhibit well-behaved capacitance-voltage characteristics, gate leakage current densities in the range of 0.01–1 A/cm2, and interface trap densities in the range of ∼3×1012 eV−1 cm−2.

We report on the improvement of electrical quality of (100)-Ge/high-k-dielectric interfaces by introducing thin Pt top layers on the dielectric and subsequent oxidative treatments or using a Pt-deposition process with inherent oxidative components. Here, deposition of thin physical vapor deposition-Pt layers, combined with subsequent oxygen treatments, or oxygen assisted atomic layer deposition of Pt on these dielectrics, is applied. Strong reduction of interface trap densities down to mid-1011 eV−1 cm−2 is achieved. The approach is shown for Pt/ZrO2/La2O3/Ge, Pt/ZrO2/GeO2/Ge, and Pt/ZrO2/Ge gate stacks. By x-ray photoelectron spectroscopy evidence is given for oxygen enrichment at Ge/high-k-dielectric interfaces, to be responsible for the improved electrical properties.

In this work, we demonstrate an approach to tune the electrical behavior of our Ω-gated germanium-nanowire (Ge-NW) MOSFETs by focused ion beam (FIB) implantation. For the MOSFETs, 35 nm thick Ge-NWs are covered by atomic layer deposition (ALD) of a high-κ gate dielectric. With the Ω-shaped metal gate acting as implantation mask, highly doped source/drain (S/D) contacts are formed in a self-aligned process by FIB implantation. Notably, without any dopant activation by annealing, the devices exhibit more than three orders of magnitude higher I(ON) currents, an improved I(ON)/I(OFF) ratio, a higher mobility and a reduced subthreshold slope of 140 mV/decade compared to identical Ge-NW MOSFETs without FIB implantation.