Imagers with programmable, highly parallel signal processing execute computationally intensive processing steps directly on the sensor, thereby allowing early reduction of the amount of data to relevant features. For the purposes of architectural exploration during development of a novel Vision-System-on-Chip (VSoC), it has been modelled on system level. Aside from the integrated control unit with multiple independent control flows, the model also realizes digital and analogue signal processing. Due to high simulation speed and compatibility with the real system, especially regarding the programs to be executed, the resulting simulation model is very well suited for usage during application development. By providing the ability to purposefully introduce parameter deviations or defects at various points of analogue processing, it becomes possible to study them with respect to their influence on image processing algorithms executed within the VSoC

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A flexible implantable solution with integrated electromyogram (EMG) and neurostimulation functions for improved control of prosthetic hands is presented. The main board of the implant is composed of two custom designed ICs, a microcontroller, an inductive power supply and a wireless communication interface. The EMG Monitor-ASIC can handle eight differential channels and provides a selectable midband gain ranging from 50-5000V/V in a bandwidth from 2Hz-1.1kHz. The input referred noise was measured to be 1.7μVrms. An adjustable 50/60Hz notch filter for suppression of power line interferences and a CMRR of more than 80dB increase the robustness of this IC. The stimulator-ASIC can be configured to deliver bipolar or monopolar current pulses through four differential electrodes with maximum amplitudes of 500μA and 1μA resolution. The stimulation profile can be configured with independent durations of each phase and a wide range of repetition rates. The eight layer PCB measures 26.0mm × 20.9mm and the ASICs are directly wire bonded to it

Designs of asynchronous networks-on-chip are of growing interest because a complete asynchronous implementation can solve the synchronization problems of large networks. However, asynchronous circuits suffer from the lack of proper design flows because their functionality often relies on timing constraints, which are not extensively supported by common CAD synthesis tools. This paper proposes the design and implementation of an asynchronous router architecture suitable for a network-on-chip in the context of a Vision-System-on-Chip. The developed design flow for the synthesis of asynchronous bundled-data pipelines is based on common synthesis tools and, therefore, enables high compatibility with synchronous designs and a low barrier to entry

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